AN-1177
APPLICATION NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
LVDS and M-LVDS Circuit Implementation Guide
by Dr. Conal Watterson
INTRODUCTION
Low voltage differential signaling (LVDS) is a standard for
communicating at high speed in point-to-point applications.
Multipoint LVDS (M-LVDS) is a similar standard for multi-
point applications. Both LVDS and M-LVDS use differential
signaling, a two-wire communication method where receivers
detect data based on the voltage difference between two
complementary electrical signals. This greatly improves noise
immunity and minimizes emissions.
LVDS/M-LVDS APPLICATION CONSIDERATIONS
This application note considers the following aspects
concerning LVDS/M-LVDS circuit implementation:
•
•
•
•
•
•
•
Bus types and topologies
Clock distribution applications
Characteristics of LVDS/M-LVDS signaling
Termination and PCB layout
Jitter and skew
Data encoding and synchronization
Isolation
LVDS
LVDS is a lower power alternative to emitter-coupled logic
(ECL) or positive emitter-coupled logic (PECL).The primary
standard for LVDS is TIA/EIA-644. An alternative standard
sometimes used for LVDS is IEEE 1596.3—SCI, scalable
coherent interface. LVDS has been widely adopted for high-
speed backplane, cabled, and board-to-board data transmission
and clock distribution, as well as communication links within a
single PCB.
Advantages of LVDS include
•
•
•
•
•
Communication at speeds of up to 1 Gbps or more
Reduced electromagnetic emissions
Increased immunity to noise
Low power operation
Common-mode range allowing differences of up to ±1 V
in ground offset
WHY USE LVDS OR M-LVDS?
LVDS and M-LVDS are compared to other multipoint and point-
to-point protocols in Figure 1. Both standards have low power
requirements. LVDS and M-LVDS are characterized by differential
signaling with a low differential voltage swing. M-LVDS specifies
an increased differential output voltage compared to LVDS in order
to allow for the increased load from a multipoint bus.
Both protocols are designed for high-speed communication.
Typical applications utilize PCB traces or short wired/backplane
links. The common mode range of LVDS is designed for these
applications. M-LVDS has an extended common mode range
compared to LVDS to allow for the additional noise in a multipoint
topology.
MULTIPOINT
M-LVDS
LOW POWER, HIGH SPEED
MEDIUM DISTANCES (MAX. 20m TO 40m)
TYP. DATA RATE: 100Mbps, 200Mbps
LONG DISTANCES (>1km)
TYP. MAX. DATA RATE: 16Mbps
ROBUST PROTOCOL
MEDIUM DISTANCES (MAX. 40m)
MAX. DATA RATE: 1Mbps
M-LVDS
The standard TIA/EIA-899 for multipoint low voltage differ-
ential signaling (M-LVDS) extends LVDS to address multipoint
applications. M-LVDS allows higher speed communication
links than TIA/EIA-485 (RS-485) or controller area network
(CAN) with lower power. See the References section for a list of
the standards referred to in this application note.
Additional features of M-LVDS over LVDS include
•
•
•
•
Increased driver output strength
Controlled transition times
Extended common-mode range
Option of failsafe receivers for bus idle condition
RS-485
CAN
POINT-TO-POINT
LVDS
LOW POWER, HIGH SPEED
SHORT DISTANCES (MAX. 5m TO 10m)
MAX. DATA RATE: >1Gbps
11236-001
PECL
HIGH SPEED
SHORT DISTANCES
MAX. DATA RATE: ~3Gbps
Figure 1. Comparison of Communication Standards
Rev. 0 | Page 1 of 12
AN-1177
TABLE OF CONTENTS
Introduction ...................................................................................... 1
LVDS/M-LVDS Application Considerations ................................ 1
Why use LVDS or M-LVDS? ........................................................... 1
Revision History ............................................................................... 2
Bus Types and Topologies ............................................................... 3
Point-to-Point ............................................................................... 3
Multi-Drop .................................................................................... 3
Multipoint ...................................................................................... 3
Clock Distribution Applications ..................................................... 4
Multi-Drop Clock Distribution .................................................. 4
Point-to-Point Clock Distribution ............................................. 4
Clock Distribution Using M-LVDS ........................................... 4
Differential Signalling and LVDS/M-LVDS .................................. 5
Application Note
Definitions and Output Levels ....................................................5
Receiver Thresholds ......................................................................5
Transmission Distance..................................................................6
Termination and PCB Layout ..........................................................7
Controlled Impedances ................................................................7
Jitter, Skew, Data Encoding, and Synchronization ........................8
What is Jitter? .................................................................................8
What is Skew? ................................................................................8
Data Encoding and Synchronization ..........................................9
Isolation ........................................................................................... 10
References ........................................................................................ 11
Related Links ............................................................................... 11
REVISION HISTORY
3/13—Revision 0: Initial Version
Rev. 0 | Page 2 of 12
Application Note
BUS TYPES AND TOPOLOGIES
Standard TIA/EIA-644 LVDS devices allow low power, high
speed communication. The advantages of LVDS can also
be applied to multipoint applications by using TIA/EIA-899
devices. Bus topology is one of the main factors relating to
which LVDS or M-LVDS devices are used in an application.
AN-1177
MULTIPOINT
In networks where multiple devices can either send or receive,
a multipoint bus topology may be used. M-LVDS is designed
for such multi-point applications, allowing up to 32 nodes to
be connected to a single bus. There are two types of multipoint
buses, half-duplex and full duplex, shown in Figure 4 and
Figure 5, respectively. In a half-duplex bus, two wires are used
such that one device may transmit, and the other devices can
receive. In a full-duplex bus, four wires are used, allowing one
node to concurrently transmit back to another transmitting
node (that is, slave devices responding as broadcast commands
are sent by the master to all nodes).
A
DI
R
T
R
OUT
11236-002
POINT-TO-POINT
Point-to-point bus topologies consist of a single driver and single
receiver connected together using one pair of wires or traces.
Figure 2 demonstrates a typical configuration, where the receiving
end of the link has a termination resistor. This is the most common
application for LVDS devices. Multiple pairs of wires or traces
can be used to create additional channels of communication and
increase total bandwidth between two points.
D
OUT+
D
IN
LVDS
DRIVER
D
OUT–
R
IN+
R
T
R
IN–
LVDS
RECEIVER
A
RO
R
T
B
DI
B
RO
Figure 2. LVDS Point-to-Point Link
Analog Devices, Inc., has a portfolio of LVDS drivers and receivers
for one, two or four LVDS channels as shown in Table 1. Unused
outputs should be left open circuit.
Table 1. LVDS Drivers and Receivers
Part No.
ADN4661
ADN4662
ADN4663
ADN4664
Tx
1
0
2
0
Rx
0
1
0
2
Part No.
ADN4665
ADN4666
ADN4667
ADN4668
Tx
4
0
4
0
Rx
0
4
0
4
DI
DI
RO
Figure 4. M-LVDS Half-Duplex Bus
Y
R
T
Z
RO
A
B
MLVDS
TRANSCEIVERS
11236-005
A
RO
R
T
B
Y
DI
R
T
R
T
Z
M-LVDS can also be used in a point-to-point topology, where the
same transceiver device is used for the driver circuit (with receiver
disabled) and the receiving circuit (with driver disabled).
DI
RO
DI
RO
Figure 5. M-LVDS Full-Duplex Bus
MULTI-DROP
A single driver can be connected to multiple receivers using
a multi-drop bus topology as shown in Figure 3. LVDS is
designed for point-to-point applications and so in a multi-drop
configuration, the number of receivers that can be connected
and the signaling distance can be limited. M-LVDS can be used
in a multi-drop topology to drive up to 32 nodes across longer
distances compared to LVDS.
D
OUT+
D
IN
LVDS
DRIVER
D
OUT–
R
IN+
R
T
R
IN–
LVDS
RECEIVERS
Another factor to be considered in multipoint buses is the bus
idle condition. When no device is transmitting, the differential
voltage on a terminated bus will be close to 0 V. This means that
for a standard receiver with symmetrical input thresholds, the
receiver output will be undefined. This corresponds to the
Type 1 M-LVDS receivers with an input threshold of ±50 mV.
In order to provide a guaranteed receiver output state (output
low) in the bus idle condition, Type 2 M-LVDS receivers have
an offset receiver input threshold of +50 mV to +150 mV.
Table 2. M-LVDS Transceivers
Part No.
ADN4690E
ADN4691E
ADN4692E
ADN4693E
ADN4694E
ADN4695E
ADN4696E
ADN4697E
Rx Type
1
1
1
1
2
2
2
2
Duplex
Half
Half
Full
Full
Half
Full
Half
Full
Data Rate
100
200
100
200
100
100
200
200
R
OUT
R
OUT
Figure 3. LVDS Multi-Drop Bus
11236-003
Rev. 0 | Page 3 of 12
11236-004
MLVDS
TRANSCEIVERS
AN-1177
CLOCK DISTRIBUTION APPLICATIONS
Differential signaling, such as LVDS, is a good choice for
distributing clock signals around a circuit board. In addition to
the benefits of the common-mode noise immunity of LVDS, a
particular advantage for clock distribution applications is that
radiated emissions are reduced due to the coupling between the
two opposing signals.
CK
SI
EN
11-BIT SHIFT
REGISTER
Application Note
12-BIT COUNTER
11-BIT CONTROL
REGISTER
10 LVDS POINT-
TO-POINT LINKS
MULTI-DROP CLOCK DISTRIBUTION
In many applications, multiple nodes in a circuit may depend
on a single clock source. A simple approach to distributing
a single clock source to multiple nodes using LVDS, is to use
a multi-drop bus topology as shown in Figure 6. The LVDS
outputs of a clock source are connected to a pair of signal traces
that have short stubs to the various nodes relying on the clock.
D
OUT+
CLK
R
T
LVDS
CLOCK
SOURCE
D
OUT–
R
IN–
LVDS
CLOCK INPUTS
11236-006
CLOCK
SOURCE
MUX
1
NODE 9
Q9
Q9
0
CLK0
CLK0
CLK1
CLK1
0
Q8
Q8
Q7
1
MUX
Q7
Q6
Q6
Q5
R
IN+
CLK
CLOCK
SOURCE
Q5
Q4
Q4
Q3
Q3
Q2
Q2
Q1
Q1
Q0
11236-007
CLK
CLK
Figure 6. Multi-Drop LVDS Clock Distribution
The disadvantages of this approach are that the number of
nodes that can be connected is limited and stubs contribute to
degradation of the signal integrity (that is, adding jitter). Stub
lengths and impedances must be carefully controlled.
ADN4670
Q0
NODE 0
POINT-TO-POINT CLOCK DISTRIBUTION
A single clock source can be connected to a single node
requiring an LVDS clock input using a point-to-point link.
This can be extended to supply multiple nodes by means of
an LVDS buffer acting as a fan-out device. This separate
component receives the LVDS clock output from the clock
source, and in turn provides this clock signal to multiple LVDS
drivers in the device to drive multiple point-to-point links to
receiving nodes. The advantage of this approach is that timing
on the clock signal can remain unaffected by stubs.
An example of such a device is the
ADN4670
clock distribution
buffer. This allows one of two clock sources to be distributed on
up to 10 outputs as shown in Figure 7. The outputs can be
enabled and disabled by means of a serially programmable
register, which is also used to select the clock source.
Figure 7.
ADN4670
Application Distributing a Clock Source to 10 Nodes via
Point-To-Point LVDS Connections
Any buffer adds a small amount of jitter when inserted between
the initial LVDS output and the eventual LVDS input, but the
ADN4670
has been designed to have low additive jitter of
<300 fs. Skew between the 10 outputs is kept to less than 30 ps
with clock signals of up to 1.1 GHz.
CLOCK DISTRIBUTION USING M-LVDS
Another option for clock distribution is using M-LVDS
transceivers to distribute the clock to up to 32 nodes in a multi-
drop (or multipoint) topology. Type 1 M-LVDS receivers (such
as in the
ADN4690E
to
ADN4693E)
are suited to such
applications because there is no offset in the receiver threshold
(this offset can result in duty cycle distortion for a clock signal).
The
ADN4690E
to
ADN4693E
M-LVDS transceivers with Type
1 receivers also have additional slew-rate limiting of the edges
from the driver outputs, which further limits radiated emissions
and the effect of reflections from stubs.
Rev. 0 | Page 4 of 12
Application Note
DIFFERENTIAL SIGNALLING AND LVDS/M-LVDS
Differential transmission is communication where two
complementary signals are transmitted, with the received signal
comprising the difference between the two signal lines. This
form of communication, used by both LVDS and M-LVDS,
has two distinct advantages, high noise immunity and low
emissions.
The high noise immunity arises because typically a noise
source couples equally onto both signal lines, leaving the
differential signal unaffected. Emissions from differential
signaling are low due to the tight coupling between the two
complementary signal lines when using a typical medium
(twisted pair cable, or closely placed strip line).
V
CC
V
CC
AN-1177
ADN4663
D
IN1
D
OUT1+
R
IN1+
100Ω
ADN4664
R
OUT1
D
OUT1–
D
OUT2+
D
IN2
D
OUT2–
GND
R
IN1–
R
IN2+
100Ω
R
IN2–
GND
R
OUT2
11236-009
Figure 9.
ADN4663
and
ADN4664
2-Channel LVDS Point-to-Point
DEFINITIONS AND OUTPUT LEVELS
For LVDS and M-LVDS, one signal line is noninverting (that is,
high for a Logic 1 and low for a Logic 0) and the other signal
line is inverting (that is, the complement of the noninverting
signal). The difference in voltage between the two signal lines
is termed the differential voltage, V
OD
. V
OD
is also shorthand for
the magnitude of the differential voltage (positive or negative),
or |V
OD
|. The two signal lines each have a maximum voltage
swing of |V
OD
|, centered on the common-mode voltage, V
OC
(also referred to as the offset voltage, V
OS
). The differential
voltage swings around 0 V. Typical LVDS signal levels are
shown in Figure 8, together with the differential signal V
OD
and common-mode voltage V
OC
. In this figure, V
OUT+
is the
noninverting signal and V
OUT−
is the inverting signal.
LOGIC 1
V
OUT+
LOGIC 0
LOGIC 1
1.35V
V
OC
= 1.2V
V
OUT–
1.05V
|V
OD
|
The distinction between LVDS and M-LVDS and other
differential signaling standards is that they have a low output
swing. The differential output voltage and common mode range
specifications of LVDS and M-LVDS are shown in Figure 10. For
LVDS, the output voltage swing, |V
OD
|, is a minimum of 250 mV
and a maximum of 450 mV with a load of 100 Ω. This allows
low power operation and ensures that while transitions are fast,
to allow high data rates, the reduced output swing means that
the slew rate is not too severe. Rise and fall times are generally
in the region of hundreds of picoseconds, resulting in slew rates
of around 0.5 V/ns to 2.5 V/ns.
M-LVDS
4V
COMMON-MODE VOLTAGE
M-LVDS
LVDS
DIFFERENTIAL OUTPUT VOLTAGE
LVDS
3V
2V
1V
0V
–1V
0V TO
2.4V
–1V TO
3.4V
250mV
450mV
480mV
650mV
MIN
V
OD
MAX
V
OD
Figure 10. LVDS and M-LVDS Signaling Levels
0.3V
|V
OD
|
V
OD
(V
OUT+
– V
OUT–
)
11236-008
0V
–0.3V
Figure 8. LVDS Output Levels
The differential voltage on an LVDS or M-LVDS bus is
generated by a driver current source. Noninverting LVDS driver
outputs or receiver inputs are generally denoted with a + and
inverting driver outputs or receiver inputs with a −.
Pin names are shown for the
ADN4663
2-channel LVDS driver
and
ADN4664
2-channel LVDS receiver in Figure 9. M-LVDS
follows the convention of RS-485 physical layer transceivers in
naming the bus lines A for the noninverting signal and B for the
inverting signal, or Y and Z for driver outputs on a full-duplex
transceiver.
M-LVDS has slew-rate limited drivers to enhance the robustness
of the signaling when there are additional impedance
discontinuities from multiple drivers/receivers and stubs. This
means that M-LVDS is limited to lower data rates compared to
LVDS. The
ADN4690E
through
ADN4697E
are available with
options for 100 Mbps or higher speed 200 Mbps. Another
characteristic of M-LVDS is increased driver strength, resulting
in a minimum output voltage swing |V
OD
| of 480 mV and a
maximum of 650 mV with a load of 50 Ω (two termination
resistors of 100 Ω, one either end of the bus).
RECEIVER THRESHOLDS
The receiver thresholds are the differential voltage levels above
or below which the received signal is considered a Logic 1 or a
Logic 0. For LVDS, a positive V
OD
>= +100 mV corresponds to
a Logic 1 and a negative V
OD
<= -100 mV corresponds to a
Logic 0.
Rev. 0 | Page 5 of 12
11236-010
MIN
V
OD
MAX
V
OD
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