Product Specification
AHA4501 Astro
36 Mbits/sec Turbo Product Code
Encoder/Decoder, 3.3V
2365 NE Hopkins Court
Pullman, WA 99163-5601
tel: 509.334.1000
fax: 509.334.9000
e-mail: sales@aha.com
www.aha.com
advancedhardwarearchitectures
This product and the algorithm are covered under multiple patents pending.
PS4501-1100
Advanced Hardware Architectures, Inc.
Table of Contents
1.0 Introduction
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Conventions, Notations and Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.0 Functional Overview
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2 Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3 Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.4 Feedback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.5 Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.6 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.6.1 Encode Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.6.2 Decode Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.6.3 Resynchronize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.7 Helical Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.8 Data Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.9 Encoding/Decoding Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.10 Summary of Channel Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.11 Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.12 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.0 Internal Register Programming
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 Configuration 0, Address 0x00 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Configuration 1, Address 0x01 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Configuration 2, Address 0x02 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4 Feedback, Address 0x03 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5 Quantization, Address 0x04 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6 Corrections, Address 0x05 - Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.7 Synchronization, Address 0x05 - Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.8 Status, Address 0x06 - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.9 Control/Interrupt, Address 0x07 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.10 Reserved, Address 0x08 - Reserved. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.0 Performance Curves
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.0 Signal Descriptions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1 System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2 Microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.3 Input Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.4 Output Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.0 Pinout
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.0 Electrical Specifications
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.2.1 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.2.2 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2.3 Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.0 Timing Specifications
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9.0 Packaging
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.0 Ordering Information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.1 Available Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.2 Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
11.0 Related Publications
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
PS4501-1100
i
Advanced Hardware Architectures, Inc.
Figures
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
Figure 6:
Figure 7:
Figure 8:
Figure 9:
Figure 10:
Figure 11:
Figure 12:
Figure 13:
Figure 14:
Figure 15:
Figure 16:
Figure 17:
Figure 18:
Figure 19:
Figure 20:
Figure 21:
Figure 22:
Figure 23:
Figure 24:
Figure 25:
Figure 26:
Figure 27:
Figure 28:
Figure 29:
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
IDATA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Input Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2D Interleaving. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Encoded/Interleaved Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Encoding at the Maximum Input Rate (bit/clock) with Maximum Output Rate (bit/clock). . . . . . . . . . . . . . . 7
Encoding at Less Than Maximum Input Rate with Maximum Output Rate . . . . . . . . . . . . . . . . . . . . . . . . . 8
Decoding with Continuous Input Data Rate - STITER not Asserted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Decoding with Burst Input Data Rate - STITER not Asserted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Decoding with Burst Input Data Rate - STITER Asserted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DUMP Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Turbo Product Code vs. Reed-Solomon/Viterbi Performance Comparison . . . . . . . . . . . . . . . . . . . . . . . . 19
Comparison of TPC Code Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Performance Curve of E
b
/N
o
for BER of 10
-5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Pinout – 100 MQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Current vs. Data Rate (typ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Signal Timing vs. Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Data Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Data Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Microprocessor Interface Timing (Write); PROCMODE=0, MUXMODE=0 . . . . . . . . . . . . . . . . . . . . . . . . 27
Microprocessor Interface Timing (Read); PROCMODE=0, MUXMODE=0 . . . . . . . . . . . . . . . . . . . . . . . . 28
Microprocessor Interface Timing (Write); PROCMODE=0, MUXMODE=1 . . . . . . . . . . . . . . . . . . . . . . . . 29
Microprocessor Interface Timing (Read); PROCMODE=0, MUXMODE=1 . . . . . . . . . . . . . . . . . . . . . . . . 30
Microprocessor Interface Timing (Write); PROCMODE=1, MUXMODE=0 . . . . . . . . . . . . . . . . . . . . . . . . 31
Microprocessor Interface Timing (Read); PROCMODE=1, MUXMODE=0 . . . . . . . . . . . . . . . . . . . . . . . . 32
Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Power On Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
AHA4501 Package Specifications – 100 MQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
ii
PS4501-1100
Advanced Hardware Architectures, Inc.
Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Table 16:
Table 17:
Recommended QSHIFT Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Channel Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Supported Codes with Recommended Feedback Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Pin Designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Data Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Data Output Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Microprocessor Interface Timing Requirements - Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Microprocessor Interface Timing Requirements - Read; PROCMODE=0, MUXMODE=0 . . . . . . . . . . . . 28
Microprocessor Interface Timing Requirements - Write; PROCMODE=0, MUXMODE=1. . . . . . . . . . . . . 29
Microprocessor Interface Timing Requirements - Read; PROCMODE=0, MUXMODE=1 . . . . . . . . . . . . 30
Microprocessor Interface Timing Requirements - Write; PROCMODE=1, MUXMODE=0. . . . . . . . . . . . . 31
Microprocessor Interface Timing Requirements - Read; PROCMODE=1, MUXMODE=0 . . . . . . . . . . . . 32
Interrupt Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Clock Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Power On Reset Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PQFP (Plastic Quad Flat Pack) 14 × 20 mm Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
PS4501-1100
iii
Advanced Hardware Architectures, Inc.
1.0
INTRODUCTION
The AHA4501 is the first single-chip Forward
Error Correction LSI device using Turbo Product
Codes (TPC). The device operates as a block code
encoder at the input or a block code decoder at the
output of a communication channel. The device
supports various programmable features, such as
block size, codes and code rates, to optimize various
communication channel needs for error
performance and data throughput. Turbo Product
Codes offer a higher performance alternative to
Reed-Solomon or Reed-Solomon concatenated
with Viterbi error correction methods.
When encoding, the device appends the Error
Correction Code (ECC) bits to the blocks, and
outputs the encoded blocks. When decoding, the
device accepts soft decision values and stores the
data as a block in its internal RAM. The block is
then decoded iteratively by running it through the
device’s soft in/soft out (SISO) decoder. The device
iterates to the maximum programmed iteration
limit. The decoded block is then output through the
device output data port.
This specification describes the functional
operation, programming, timing and ordering
information. Please contact AHA for additional
support material, including evaluation software and
relevant technical publications; or visit our website
at http://www.aha.com.
– Intermediate Storage Array (ISA) – The storage
array for data between iterating.
– Hard Decision Array (HDA) – The hard decision
output. Data is stored as one bit per location.
– (n
1
,k
1
)x(n
2
,k
2
) – A general representation of a 2D
block code for use in the descriptions to follow in
this specification. For example, in a
(64,57)x(64,57) code; n
1,
n
2
=64 represents the
length of the data + ECC bits, and k
1
,k
2
=57
represents the length of only the data bits. 3D
codes are represented as (n
1
,k
1
)x(n
2
,k
2
)x(n
3
,k
3
)
– Vector – One row or column of data in a block.
– Latency – The time from the first bit of a block in
to first bit of the same block out.
– Active low signals have an “N” appended to the
end of the signal name. For example, MCSN and
RESETN.
– Hex values are represented with a prefix of “0x”,
such as register “0x00”. Binary values do not
contain a prefix.
1.2
FEATURES
1.1
CONVENTIONS, NOTATIONS AND
DEFINITIONS
– Code block – A data stream to be encoded or
decoded is segmented into blocks for processing
by the AHA4501. Data in a code block is
configured as a 2D or 3D array.
– Axis iteration – Decoding one axis of an array (all
x rows, all y columns, or all z columns).
– Full iteration – Decoding all axes of an array (all
rows and columns).
– Soft value – Input to the decoder from either an
Analog/Digital Converter(ADC) or digital
demodulator.
– Code rate – Ratio of the number of data bits to the
number of data and ECC bits.
– Data rate – The rate at which unencoded data is
input to the device when encoding or output from
the device when decoding.
– Channel Rate – The rate at which encoded data is
output from the device when encoding or input to
the device when decoding. Note that system
channel rate may be different due to external
synchronization marks or other overhead.
– Original Array (OA) – The soft decision input data
array. Data is stored as a 6 bit soft value per location
to support the maximum 6 bit input quantization.
PS4501-1100
PERFORMANCE:
• Maximum 50 Mbits/sec channel rate encoding
• 36.5 Mbits/sec channel rate decoding for a 64x57
square code at two iterations
• Two or more devices can be used in parallel to
increase throughput
• Optional “helical” interleaving (encoding) and
deinterleaving (decoding)
FLEXIBILITY:
• Internal buffering allows continuous data
streaming
• Programmable block size from 256 to 4096 bits
• Two or three dimensional blocks
• Programmable number of iterations per block up
to 32
• Programmable quantization up to 6-bits for soft or
hard decision input data (decoding)
• Support for external synchronization
SYSTEM INTERFACE:
• Serial or 8-bit parallel input and output data ports
• Selectable microprocessor interface for Intel or
Motorola processors
• Control Commands for: Decode, Encode, Soft
Reset, Resynchronize and Dump Current Block
• System Interrupts include Block Decode Complete,
Block Correction Incomplete, Sync Mark Mismatch
• Number of corrections per block accumulated in
an internal register
OTHERS:
• 3.3 Volt operation
• 100 pin quad flat package
• Output signals may be tristated to facilitate board
level testing
Page 1 of 36
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
