Spansion
®
Analog and Microcontroller
Products
The following document contains information on Spansion analog and microcontroller products. Although the
document is marked with the name “Fujitsu”, the company that originally developed the specification, Spansion
will continue to offer these products to new and existing customers.
Continuity of Specifications
There is no change to this document as a result of offering the device as a Spansion product. Any changes that
have been made are the result of normal document improvements and are noted in the document revision
summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a
revision summary.
Continuity of Ordering Part Numbers
Spansion continues to support existing part numbers beginning with “MB”. To order these products, please use
only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local sales office for additional information about Spansion memory, analog, and
microcontroller products and solutions.
FUJITSU SEMICONDUCTOR
DATA SHEET
DS704-00003-2v0-E
16-bit Proprietary Microcontroller
2
F MC-16FX MB96650 Series
MB96F653R/A, MB96F655R/A
MB96F656R, MB96F657R
DESCRIPTION
MB96650 series is based on FUJITSU’s advanced F
2
MC-16FX architecture (16-bit with instruction
pipeline for RISC-like performance). The CPU uses the same instruction set as the established F
2
MC-16LX
family thus allowing for easy migration of F
2
MC-16LX Software to the new F
2
MC-16FX products.
F
2
MC-16FX product improvements compared to the previous generation include significantly improved
performance - even at the same operation frequency, reduced power consumption and faster start-up time.
For high processing speed at optimized power consumption an internal PLL can be selected to supply the
CPU with up to 32MHz operation frequency from an external 4MHz to 8MHz resonator. The result is a
minimum instruction cycle time of 31.2ns going together with excellent EMI behavior. The emitted power
is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree
allows selecting suitable operation frequencies for peripheral resources independent of the CPU speed.
Note: F
2
MC is the abbreviation of FUJITSU Flexible Microcontroller.
FUJITSU SEMICONDUCTOR provides information facilitating product development via the following website.
The website contains information useful for customers.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2011-2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2013.6
MB96650 Series
FEATURES
•
Technology
•
CPU
0.18µm CMOS
•
F
2
MC-16FX CPU
•
Optimized instruction set for controller applications
(bit, byte, word and long-word data types, 23 different addressing modes, barrel shift, variety of pointers)
•
8-byte instruction queue
•
Signed multiply (16-bit
×
16-bit) and divide (32-bit/16-bit) instructions available
•
System clock
•
On-chip PLL clock multiplier (×1 to
×8, ×1
when PLL stop)
•
4MHz to 8MHz crystal oscillator
(maximum frequency when using ceramic resonator depends on Q-factor)
•
Up to 8MHz external clock for devices with fast clock input feature
•
32.768kHz subsystem quartz clock
•
100kHz/2MHz internal RC clock for quick and safe startup, clock stop detection function, watchdog
•
Clock source selectable from mainclock oscillator, subclock oscillator and on-chip RC oscillator,
independently for CPU and 2 clock domains of peripherals
•
The subclock oscillator is enabled by the Boot ROM program controlled by a configuration marker after a
Power or External reset
•
Low Power Consumption - 13 operating modes (different Run, Sleep, Timer, Stop modes)
Internal voltage regulator supports a wide MCU supply voltage range (Min=2.7V), offering low power
consumption
Reset is generated when supply voltage falls below programmable reference voltage
Protects Flash Memory content from unintended read-out
Automatic transfer function independent of CPU, can be assigned freely to resources
•
On-chip voltage regulator
•
Low voltage detection function
•
Code Security
•
DMA
•
Interrupts
•
Fast Interrupt processing
•
8 programmable priority levels
•
Non-Maskable Interrupt (NMI)
•
Supports CAN protocol version 2.0 part A and B
•
ISO16845 certified
•
Bit rates up to 1Mbps
•
32 message objects
•
Each message object has its own identifier mask
•
Programmable FIFO mode (concatenation of message objects)
•
Maskable interrupt
•
Disabled Automatic Retransmission mode for Time Triggered CAN applications
•
Programmable loop-back mode for self-test operation
•
CAN
2
DS704-00003-2v0-E
MB96650 Series
•
USART
•
Full duplex USARTs (SCI/LIN)
•
Wide range of baud rate settings using a dedicated reload timer
•
Special synchronous options for adapting to different synchronous serial protocols
•
LIN functionality working either as master or slave LIN device
•
Extended support for LIN-Protocol to reduce interrupt load
•
Up to 400kbps
•
Master and Slave functionality, 7-bit and 10-bit addressing
•
I
2
C
•
A/D converter
•
SAR-type
•
8/10-bit resolution
•
Signals interrupt on conversion end, single conversion mode, continuous conversion mode,
stop conversion mode, activation by software, external trigger, reload timers and PPGs
•
Range Comparator Function
•
Scan Disable Function
Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit Sub clock timer)
•
Source Clock Timers
•
Hardware Watchdog Timer
•
Hardware watchdog timer is active after reset
•
Window function of Watchdog Timer is used to select the lower window limit of the watchdog interval
•
Reload Timers
•
16-bit wide
•
Prescaler with 1/2
1
, 1/2
2
, 1/2
3
, 1/2
4
, 1/2
5
, 1/2
6
of peripheral clock frequency
•
Event count function
•
Signals an interrupt on overflow, supports timer clear upon match with Output Compare (0, 4)
•
Prescaler with 1, 1/2
1
, 1/2
2
, 1/2
3
, 1/2
4
, 1/2
5
, 1/2
6
, 1/2
7
, 1/2
8
of peripheral clock frequency
•
16-bit wide
•
Signals an interrupt upon external event
•
Rising edge, Falling edge or Both (rising & falling) edges sensitive
•
16-bit wide
•
Signals an interrupt when a match with Free-running Timer occurs
•
A pair of compare registers can be used to generate an output signal
•
Free-Running Timers
•
Input Capture Units
•
Output Compare Units
•
Programmable Pulse Generator
•
16-bit down counter, cycle and duty setting registers
•
Can be used as 2
×
8-bit PPG
•
Interrupt at trigger, counter borrow and/or duty match
•
PWM operation and one-shot operation
•
Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock or of selected Reload timer
underflow as clock input
•
Can be triggered by software or reload timer
•
Can trigger ADC conversion
•
Timing point capture
•
Start delay
DS704-00003-2v0-E
3
MB96650 Series
•
Quadrature Position/Revolution Counter (QPRC)
•
Up/down count mode, Phase difference count mode, Count mode with direction
•
16-bit position counter
•
16-bit revolution counter
•
Two 16-bit compare registers with interrupt
•
Detection edge of the three external event input pins AIN, BIN and ZIN is configurable
•
Operational on main oscillation (4MHz), sub oscillation (32kHz) or RC oscillation (100kHz/2MHz)
•
Capable to correct oscillation deviation of Sub clock or RC oscillator clock (clock calibration)
•
Read/write accessible second/minute/hour registers
•
Can signal interrupts every half second/second/minute/hour/day
•
Internal clock divider and prescaler provide exact 1s clock
•
Edge or Level sensitive
•
Interrupt mask bit per channel
•
Each available CAN channel RX has an external interrupt for wake-up
•
Selected USART channels SIN have an external interrupt for wake-up
•
Disabled after reset, can be enabled by Boot-ROM depending on ROM configuration block
•
Once enabled, can not be disabled other than by reset
•
High or Low level sensitive
•
Pin shared with external interrupt 0
•
Real Time Clock
•
External Interrupts
•
Non Maskable Interrupt
•
I/O Ports
•
Most of the external pins can be used as general purpose I/O
•
All push-pull outputs (except when used as I
2
C SDA/SCL line)
•
Bit-wise programmable as input/output or peripheral signal
•
Bit-wise programmable input enable
•
One input level per GPIO-pin (either Automotive or CMOS hysteresis)
•
Bit-wise programmable pull-up resistor
•
Built-in On Chip Debugger (OCD)
•
One-wire debug tool interface
•
Break function:
- Hardware break: 6 points (shared with code event)
- Software break: 4096 points
•
Event function
- Code event: 6 points (shared with hardware break)
- Data event: 6 points
- Event sequencer: 2 levels + reset
•
Execution time measurement function
•
Trace function: 42 branches
•
Security function
•
Dual operation flash allowing reading of one Flash bank while programming or erasing the other bank
•
Command sequencer for automatic execution of programming algorithm and for supporting DMA for
programming of the Flash Memory
•
Supports automatic programming, Embedded Algorithm
•
Write/Erase/Erase-Suspend/Resume commands
•
A flag indicating completion of the automatic algorithm
•
Erase can be performed on each sector individually
•
Sector protection
•
Flash Security feature to protect the content of the Flash
•
Low voltage detection during Flash erase or write
DS704-00003-2v0-E
•
Flash Memory
4
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