SN54ACT563, SN74ACT563
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS550B – NOVEMBER 1995 – REVISED OCTOBER 2002
D
D
D
D
D
D
4.5-V to 5.5-V V
CC
Operation
Inputs Accept Voltages to 5.5 V
Max t
pd
of 8.5 ns at 5 V
Inputs Are TTL-Voltage Compatible
3-State Inverted Outputs Drive Bus Lines
Directly
Flow-Through Architecture to Optimize
PCB Layout
SN54ACT563 . . . J OR W PACKAGE
SN74ACT563 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
description/ordering information
The ’ACT563 devices are octal D-type
transparent latches with 3-state outputs. When
the latch-enable (LE) input is high, the Q outputs
are set to the complements of the data (D) inputs.
When LE is taken low, the Q outputs are latched
at the inverse logic levels set up at the D inputs.
A buffered output-enable (OE) input places the
eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In
the high-impedance state, the outputs neither
load nor drive the bus lines significantly. The
high-impedance state and increased high logic
level provide the capability to drive bus lines
without interface or pullup components.
OE does not affect internal operations of the
latches. Old data can be retained or new data can
be entered while the outputs are in the
high-impedance state.
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
SN54ACT563 . . . FK PACKAGE
(TOP VIEW)
2D
1D
OE
V
CC
3D
4D
5D
6D
7D
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
1Q
2Q
3Q
4Q
5Q
6Q
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PDIP – N
SOIC – DW
–40°C to 85°C
40°C
SOP – NS
SSOP – DB
TSSOP – PW
CDIP – J
–55°C to 125°C
CFP – W
LCCC – FK
PACKAGE†
Tube
Tube
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tube
Tube
Tube
ORDERABLE
PART NUMBER
SN74ACT563N
SN74ACT563DW
SN74ACT563DWR
SN74ACT563NSR
SN74ACT563DBR
SN74ACT563PWR
SNJ54ACT5634J
SNJ54ACT563W
SNJ54ACT563FK
TOP-SIDE
MARKING
SN74ACT563N
ACT563
ACT563
AD563
AD563
SNJ54ACT563J
SNJ54ACT563W
SNJ54ACT563FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
2002, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
•
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8D
GND
CLK
8Q
7Q
1
SN54ACT563, SN74ACT563
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS550B – NOVEMBER 1995 – REVISED OCTOBER 2002
FUNCTION TABLE
(each latch)
INPUTS
OE
L
L
L
H
LE
H
H
L
X
D
H
L
X
X
OUTPUT
Q
L
H
Q0
Z
logic diagram (positive logic)
OE
LE
1
11
C1
1D
2
1D
19
1Q
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
CC
+ 0.5 V
Output voltage range, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
CC
+ 0.5 V
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±200
mA
Package thermal impedance,
θ
JA
(see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SN54ACT563, SN74ACT563
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS550B – NOVEMBER 1995 – REVISED OCTOBER 2002
recommended operating conditions (see Note 3)
SN54ACT563
MIN
VCC
VIH
VIL
VI
VO
IOH
IOL
∆t/∆v
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
Output voltage
High-level output current
Low-level output current
Input transition rise or fall rate
0
0
4.5
2
0.8
VCC
VCC
–24
24
8
0
0
MAX
5.5
SN74ACT563
MIN
4.5
2
0.8
VCC
VCC
–24
24
8
MAX
5.5
UNIT
V
V
V
V
V
mA
mA
ns/V
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –50
µA
50
VOH
IOH = –24 mA
24
IOH = –50 mA†
IOH = –75 mA†
IOL = 50
µA
VOL
IOL = 24 mA
IOL = 50 mA†
IOL = 75 mA†
IOZ
II
ICC
∆I
CC‡
Ci
VO = VCC or GND
VI = VCC or GND
VI = VCC or GND,
IO = 0
One input at 3.4 V,
Other inputs at GND or VCC
VCC
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
0.6
±0.25
±0.1
4
±5
±1
80
1.6
0.001
0.001
0.1
0.1
0.36
0.36
0.1
0.1
0.5
0.5
1.65
1.65
±2.5
±1
40
1.5
µA
µA
µA
mA
pF
TA = 25°C
MIN
TYP
MAX
4.4
5.4
3.86
4.86
4.49
5.49
SN54ACT563
MIN
4.4
5.4
3.7
4.7
3.85
3.85
0.1
0.1
0.44
0.44
V
MAX
SN74ACT563
MIN
4.4
5.4
3.76
4.76
V
MAX
UNIT
VI = VCC or GND
5V
4.5
† Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.
‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
timing requirements over recommended operating free-air temperature range, V
CC
= 5 V
±
0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
tw
tsu
th
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
3
4
0
SN54ACT563
MIN
5
4.5
1.5
MAX
SN74ACT563
MIN
3
4.5
0
MAX
UNIT
ns
ns
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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SN54ACT563, SN74ACT563
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS550B – NOVEMBER 1995 – REVISED OCTOBER 2002
switching characteristics over recommended operating
V
CC
= 5 V
±
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
D
LE
TO
(OUTPUT)
Q
Q
Q
Q
free-air
temperature
SN74ACT563
MIN
2.5
2.5
2.5
2
2
2
2.5
1
MAX
12.5
11
11.5
10.5
10
9.5
11.5
8.5
range,
UNIT
ns
ns
ns
ns
TA = 25°C
MIN
TYP
MAX
3
3
3
2.5
2.5
2
3.5
2
7
6
6.5
5.5
5.5
5.5
6.5
4.5
11.5
10
10.5
9.5
9
8.5
10.5
8
SN54ACT563
MIN
1
1
1
1
1
1
1
1
MAX
14.5
12
12.5
11.5
11.5
11
12
9.5
OE
OE
operating characteristics, V
CC
= 5 V, T
A
= 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
CL = 50 pF,
f = 1 MHz
TYP
50
UNIT
pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54ACT563, SN74ACT563
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS550B – NOVEMBER 1995 – REVISED OCTOBER 2002
PARAMETER MEASUREMENT INFORMATION
2
×
VCC
From Output
Under Test
CL = 50 pF
(see Note A)
500
Ω
S1
Open
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
2
×
VCC
Open
500
Ω
LOAD CIRCUIT
3V
Timing Input
tw
3V
Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Data Input
tsu
1.5 V
1.5 V
0V
th
3V
1.5 V
0V
Output
Control
(low-level
enabling)
tPZL
3V
Input
tPLH
Output
50% VCC
VOLTAGE WAVEFORMS
1.5 V
1.5 V
0V
tPHL
VOH
50% VCC
VOL
Output
Waveform 2
S1 at Open
(see Note B)
Output
Waveform 1
S1 at 2
×
VCC
(see Note B)
tPZH
3V
1.5 V
1.5 V
0V
tPLZ
≈V
CC
50% VCC
VOL + 0.3 V
tPHZ
50% VCC
VOH – 0.3 V
VOH
≈0
V
VOL
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
1 MHz, ZO = 50
Ω,
tr
≤
2.5 ns, tf
≤
2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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5
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