SYNC frequency = 50MHz. All bits loaded with 50Ω Thevenin
termination and 20pF
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
3. Per TTL driven input. All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. It is derived with Q frequency as the reference.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+ DI
CC
D
H
N
T
+ I
CCD
(f) + I
LOAD
I
CC
= Quiescent Current (I
CCL
,
I
CCH
and I
CCZ
)
ΔI
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f = 2Q Frequency
I
LOAD
= Dynamic Current due to load.
Test Conditions
(1)
V
IN
= V
CC
–0.6V
(3)
V
IN
= V
CC
V
IN
= GND
Min.
—
—
—
—
Typ.
(2)
2
0.2
15
30
Max.
30
0.3
25
60
Unit
µA
mA/
MHz
pF
mA
—
90
120
mA
SYNCH INPUT TIMING REQUIRMENTS
Symbol
T
RISE/FALL
Parameter
Rise/Fall Times, SYNC inputs
(0.8V to 2V)
Frequency Input Frequency, SYNC Inputs
Duty Cycle Input Duty Cycle, SYNC Inputs
10
(1)
25%
2Q fmax
75%
MHz
—
Min.
—
Max.
3
Unit
ns
OUTPUT FREQUENCY SPECIFICATIONS
Max.
(2)
Symbol
f2Q
fQ
fQ/2
Parameter
Operating frequency 2Q Output
Operating frequency Q0-Q4,
Q5
Outputs
Operating frequency Q/2 Output
Min.
40
20
10
70
70
35
17.5
100
100
50
25
133
(3)
133
66.7
33.3
150
(3)
150
75
37.5
Unit
MHz
MHz
MHz
NOTES:
1. Note 7 in "General AC Specification Notes" and Figure 3 describes this specification and its actual limits depending on the feedback connection.
2. Maximum operating frequency is guaranteed with the part in a phase locked condition and all outputs loaded.
3. At this frequency, 2Q cannot be used as feedback.
3. These specifications are guaranteed but not production tested.
4. Under equally loaded conditions, as specified under test conditions and at a fixed temperature and voltage.
5. t
CYCLE
= 1/frequency at which each output (Q,
Q,
Q/2 or 2Q) is expected to run.
6. With V
CC
fully powered-on and an output properly connected to the FEEDBACK pin, t
LOCK
Max. is with C1 = 0.1µF, t
LOCK
Min. is with C1 = 0.01µF. (Where C1 is loop filter
capacitor shown in Figure 2).
7. The wiring diagrams and written explanations of Figure 3 demonstrate the input and output frequency relationships for various possible feedback configurations. The allowable
SYNC input range to stay in the phase-locked condition is also indicated. There are two allowable SYNC frequency ranges, depending on whether FREQ_SEL is HIGH or LOW.
Also it is possible to feed back the
Q5
output, thus creating a 180° phase shift between the SYNC input and the Q outputs. The table below summarizes the allowable SYNC
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