SM2405 - Enhanced SDRAM
512Kx32 ESDRAM
Product Brief
Features
•
100% Function and Timing Compatible with JEDEC
standard SDRAM
•
Pin Compatible with JEDEC Std. SGRAM
•
Integrated 8Kbit SRAM Row Cache per Bank
•
Synchronous Operation up to 150MHz
•
24ns Row Access Latency, 10ns Column Latency
•
Two Bank Architecture
s
1K rows x 256 column x 32 bits x 2 banks
•
Early Auto-Precharge
•
Programmable Burst Length (1, 2, 4, 8, full page)
•
Programmable CAS Latency (1, 2, 3)
•
Hidden Auto-Refresh without closing Read Pages
•
Low Power Suspend, Self-Refresh, and Power Down
Modes Supported
•
Optional “No Write Transfer” Mode
•
Optional Read DQM Latency = 1 for CL=1 (EMRS)
•
Single 3.3V Power Supply
•
Flexible V
DDQ
Supports LVTTL and 2.5V I/O
•
Programmable Output Impedance (EMRS)
•
2K / 32ms Refresh
•
100-pin LQFP (0.65mm pin pitch)
Description
The SM2405 Enhanced SDRAM (ESDRAM) is a single
data rate I/O device which combines raw speed with
innovative
architecture
to
optimize
system
price/performance in high performance video graphics
and embedded systems. The device is pin compatible
with industry standard SGRAM. It is also function and
timing compatible with JEDEC standard SDRAMs.
The two bank architecture combines 24ns DRAM arrays
with a 10ns SRAM row cache per bank. The SM2405 is a
superset technology of JEDEC standard SDRAM. Its two
key functional features include early auto-precharge (close
DRAM page while burst reads are performed) and an
optional No Write Transfer mode. The ESDRAM is
capable of maintaining two open read pages and two open
write pages simultaneously via the No Write Transfer
mode.
FUNCTIONAL BLOCK DIAGRAM
ADDRESS BUFFERS
ROW DECODER
BA
A(9:0)
BANK A
1K rows x
256 col x
32 bits
BANK B
1K rows x
256 col x
32 bits
DATA LATCHES
SENSE AMPLIFIERS
SENSE AMPLIFIERS
SRAM ROW CACHE
COLUMN DECODER
SRAM ROW CACHE
COLUMN DECODER
CLK
CKE
/CS
/RAS
/CAS
/WE
DQM(3:0)
COMMAND
DECODER
and
TIMING
GENERATOR
DQ(31:0)
The information contained herein is subject to change without notice.
Enhanced reserves the right to change or discontinue this product
without notice.
©
1999 Enhanced Memory Systems Inc.
1850 Ramtron Drive, Colorado Springs, CO 80921
Telephone
(800) 545-DRAM,
Fax
(719) 488-9095,
Web
http://www.edram.com
Rev. 2.1
DATA LATCHES
SM2405 - 512Kx32 ESDRAM
Architecture
The ESDRAM architecture combines two banks of fast
24ns DRAM with two banks of 11ns SRAM row register
cache on one chip to improve memory latency. On a page
read miss, a DRAM bank is activated and data is
developed by the DRAM sense amplifiers in 13.3ns. The
sense amplifiers now hold an entire row of data (8K bits).
On a read command, the entire row is latched into the
SRAM row register and the specified starting address is
output in 10ns (CAS Latency 1 at clock frequencies up to
83MHz, and CAS Latency 2 up to 150MHz). The
architecture allows fast 11ns latency to any of the
constantly open rows on page hits.
Early auto-precharge can be performed since row data is
latched separately in the SRAM row cache from the
DRAM sense amplifiers. The precharge time can be
hidden behind a burst read from cache. This minimizes
subsequent page miss latency. The auto-precharge begins
one clock cycle after the Read-Autoprecharge command
and completes early enough to allow the next pipelined
random access to complete by the end of the current burst
cycle.
At 150MHz, all but one cycle of the next random access
PINOUT
VSSQ
DQ1
DQ30
VSSQ
DQ29
VSS
DQ31
DQ0
VDD
DQ2
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
DQ16
DQ17
VSSQ
DQ18
DQ19
VDDQ
VDD
VSS
DQ20
DQ21
VSSQ
DQ22
DQ23
VDDQ
DQM0
DQM2
/WE
/CAS
/RAS
/CS
BA
A8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQ28
VDDQ
DQ27
DQ26
VSSQ
DQ25
DQ24
VDDQ
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
VSS
VDD
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
NC
DQM3
DQM1
CLK
CKE
NC
NC
A9/AP
to any location in the same bank can be hidden to increase
sustained bandwidth by up to two times over standard
SDRAM. For interleaved burst read accesses, the entire
precharge time is hidden and output data can be driven
without any wait states.
The ESDRAM architecture also offers the designer two
different cache load strategies via the mode register set for
write cycles. In Write Transfer mode, the row register
cache is always loaded with the sense amplifier (DRAM
data) contents on a write command. This ensures
coherency between the row cache and the DRAM array.
This allows read-modify-write cycles and simplified
memory control logic.
In No Write Transfer mode, the row register cache is not
loaded during writes. Data is written to the DRAM sense
amplifiers and the prior row contents are maintained in
the row cache (for write page misses). If the on-chip page
hit/miss comparator determines that the write is to the
same row latched in the SRAM row cache, the write
updates the row cache as well as the DRAM sense
amplifiers to maintain coherency. No Write Transfer
mode allows immediate return to the prior cached read
page without otherwise incurring a page miss penalty.
Write page precharge and a bank activate times can be
hidden during cache reads. The ESDRAM’s fast
precharge time minimizes latency between the
end of a write and the next read or write miss
cycle. If a cache read follows a write cycle, write
precharge time can be hidden.
The synchronous interface of the ESDRAM
allows operation at clock rates up to 150MHz
with 2.5V I/O levels. Fast input set-up and clock-
to-output times allow actual system operation at
the specified clock rate.
Compatibility
By making the ESDRAM exactly pin-compatible
with JEDEC standard SDRAM, it is possible for
the memory controller to support both types of
memory with a simple mode selection. Both
SDRAM and ESDRAM use identical memory
footprints on the planar and identical SO-DIMM
module wiring. Systems designed to support both
memory types can provide two distinct
price/performance points and a simple field
upgrade with the ESDRAM.
100 PIN LQFP
14 x 20 mm body
0.65 mm pitch
A0
A1
A2
VSS
A4
A5
A3
VDD
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A6
A7
2
Rev. 2.1
SM2405 - 512Kx32 ESDRAM
Basic Operating Modes
The ESDRAM operating modes are specified in the
following text and in the table below.
Burst Terminate -
The ESDRAM terminates a burst
read after a delay equal to the CAS latency. It will
terminate a burst write and mask data in the current cycle.
Single Bank Precharge -
The ESDRAM will perform
a manual precharge of the bank specified by BA while
A9/AP is low. Manual precharge terminates a burst read
after a delay equal to the CAS latency.
It will also
terminate a burst write and mask data in the current cycle.
Precharge All Banks -
The ESDRAM will precharge
both open banks if A9/AP is high. It will terminate burst
cycles exactly the same as the Single Bank Precharge
command.
Auto Refresh (CBR) -
The ESDRAM will perform an
internal refresh cycle on both DRAM banks. Both banks
must be closed before this command is executed. Unlike
standard SDRAM, this command can be executed while
performing cache burst reads. The contents of each row
cache are not lost during Auto Refresh cycles.
Self Refresh Entry -
The ESDRAM enters a self
refresh mode with refresh cycles automatically generated
by an internal clock. Self Refresh mode continues as long
as CKE is low. All input buffers except CKE are disabled.
The chip is in a low power standby mode.
Device Deselect -
When /CS is high, the command
decoder is disabled but the prior command will be
completed (i.e. a burst will complete).
Clock Suspend/Standby Mode -
When CKE is low,
the internal execution of the current command is
suspended until CKE returns high.
Power Down Entry/Exit -
If both DRAM banks are
precharged, CKE is low, and /CS is high, the chip will
enter its power down mode. Once the chip is in power
down mode, the chip will exit power down mode one clock
after CKE is returned high.
Data Write/Output Enable -
When DQM is low, write
data is written to the chip during a write command and the
output buffers are enabled during read commands. In
standard mode, DQM latency is two cycles for reads and
zero cycles for writes. In the optional mode (see EMRS),
DQM latency is one cycle for reads only when CAS
latency is set to 1.
Data Mask/Output Disable -
When DQM is high,
write data is masked during a write command and the
output buffers are disabled during read commands. In
standard mode, DQM latency is two cycles for reads and
zero cycles for writes. In the optional mode (see EMRS),
DQM latency is one cycle for reads only when CAS
latency is set to 1.
3
Rev. 2.1
Hit and Miss Terminology -
“Hit” and “miss” refer to
whether or not a new row address presented to the
ESDRAM matches a row already activated in the device.
There are up to two rows or “pages” that can be open at
any given point in time. The row data or page contents
consist of 8192 bits or 256 32-bit words and are held in
each bank’s sense amplifiers. Each page is selected by the
bank select pin BA. Each bank’s SRAM row cache is
loaded only when a read command is issued. The
ESDRAM’s on-chip row address comparator is used only
in No Write Transfer mode of operation.
The memory controller typically stores row or page
address tags in order to determine which command to
issue based on the tag compare result.
Mode Register Set -
Two mode registers are loaded
from pins BA and A9-A0 when /CS, /RAS, /CAS, and
/WE are low. The standard mode register specifies the
burst length, burst type, CAS latency, and write transfer
mode. The standard mode register is set by issuing an
MRS command while BA is low. Read DQM latency
mode and output driver impedance are optionally set via
the extended mode register (EMRS). The extended mode
register is set by issuing an MRS command while BA is
high.
Bank Activate -
BA specifies one of the two banks and
the row address A9-A0 specifies which of the 1024 rows
to load into its sense amplifiers. In No Write Transfer
mode, the ESDRAM compares the last row read address to
the current row address. If the two row addresses match, a
subsequent write updates the SRAM row cache in addition
to the DRAM. Otherwise, only the DRAM is written.
Write -
The ESDRAM performs a write or burst write to
the bank specified by BA and begins writing at the start
address specified by the column address A7-A0. If the
A9/AP pin is high, the auto-precharge operation begins
one cycle following the last write of the burst. Note: In No
Write Transfer mode, if the on-chip hit/miss comparator
result (from ACTV cycle) indicates a page hit, then the
write is performed to both the row cache and the DRAM.
Read -
The ESDRAM loads the row cache and performs
a read or burst read from the cache to the bank specified
by BA and begins reading at the start address specified by
the column address A7-A0. If the A9/AP pin is high, the
auto-precharge operation begins one cycle following this
command. The first read data is output from the memory
after the CAS latency (defined by the Mode Register Set)
has been satisfied.
SM2405 - 512Kx32 ESDRAM
ESDRAM Command Truth Table
CKE
Function
Mode Register Set
Extended Mode Register Set
Bank Activate
Write with Auto-Precharge
Write
Read with Auto-Precharge
Read
Burst Termination
Single Bank Precharge
Precharge All Banks
Auto-Refresh (CBR)
Self Refresh Entry
Self Refresh Exit
No Operation
Device Deselect
Clock Suspend/Standby
Power Down Mode Entry
Power Down Mode Exit
Data Write/Output Enable
Data Mask/Output Disable
Previous
Cycle
Current
Cycle
/CS
L
L
L
L
L
L
L
L
L
L
L
L
/RAS
L
L
L
H
H
H
H
H
L
L
L
L
/CAS
L
L
H
L
L
L
L
H
H
H
L
L
/WE
L
L
H
L
L
H
H
L
L
L
H
H
DQM
X
X
X
X
X
X
X
X
X
X
X
X
X
BA
L
H
BS
BS
BS
BS
BS
X
BS
X
X
X
X
X
X
X
X
X
X
X
A9/AP
A8
Op Code
Op Code
A7-A0
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
L
H
L
H
H
X
X
X
X
X
X
X
X
X
X
H
L
H
X
X
X
L
H
X
X
Row Address
H
L
H
L
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Column
Column
Column
Column
X
X
X
X
X
X
X
X
X
X
X
X
X
NOP or DESEL
L
H
X
H
X
X
H
X
X
H
X
X
X
X
X
X
X
NOP or DESEL
NOP or DESEL
X
X
X
X
X
X
X
X
L
H
Pin Description
Symbol
CLK
CKE
/CS
Type
Input
Input
Input
Function
Clock: All ESDRAM input signals are sampled on the positive edge of CLK.
Clock Enable: Activates the CLK signal when high and deactivates CLK internally. CKE low initiates the
Power Down, Suspend, and Self-Refresh modes.
Chip Select: Active low /CS enables the command decoder and disables the command decoder when
high. When the command decoder is disabled, new commands are ignored but previous operations
continue.
Command Inputs: Sampled on the rising edge of CLK, these inputs define the command to be executed.
Bank Address: This input defines to which of the 2 banks a given command is being applied. This
address input is also used to program the Mode Registers.
Address Inputs: A9-A0 defines the row address for the Bank Activate command. A7-A0 defines the
column address for Read and Write commands. A9/AP invokes the Auto-Precharge operation. During
manual Precharge commands, A9/AP low specifies a single bank precharge while A9/AP high precharges
all banks. The address inputs are also used to program the Mode Registers.
Data I/O: Data bus inputs and outputs. For Write cycles, input data is applied to these pins and must be
set-up and held relative to the rising edge of clock. For Read cycles, the device drives output data on
these pins after the CAS latency is satisfied.
Data I/O Mask Inputs: DQM inputs mask write data (zero latency) and acts as a synchronous output
enable (2 cycle latency) for read data. In the optional mode set via the Extended Mode Register, output
enable latency is one when CAS latency is one.
Power (+3.3V) and ground for the input buffers and core logic.
Isolated power supply and ground for output buffers. V
DDQ
may be connected to either 3.3V or 2.5V power.
/RAS, /CAS, /WE
BA
A9-A0
Input
Input
Input
DQ31-DQ0
Input/
Output
Input
DQM3-DQM0
V
DD
, V
SS
V
DDQ
, V
SSQ
Supply
Supply
4
Rev. 2.1
SM2405 - 512Kx32 ESDRAM
Mode Register Set (Address Input for Mode Set)
BA
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Operation Mode
CAS Latency
BT
Burst Length
BA
0
0
M9
0
1
M8
0
0
M7
0
0
Mode
Write
Transfer
No Write
Transfer
M3
0
1
Burst Type
Sequential
Interleaved
Burst Length
M6
0
0
0
0
1
1
1
1
M5
0
0
1
1
0
0
1
1
M4
0
1
0
1
0
1
0
1
Reserved
1
2
3
Reserved
Reserved
Reserved
Reserved
M2
0
0
0
0
1
1
1
1
M1
0
0
1
1
0
0
1
1
M0
0
1
0
1
0
1
0
1
Sequential
1
2
4
8
Reserved
Reserved
Reserved
Full Page
Interleaved
1
2
4
8
Reserved
Reserved
Reserved
Reserved
Extended Mode Register Set (Address Input for Mode Set)
BA
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Mode
DQM
Reserved
O/P Z
Rsvd
BA
1
1
M9
0
1
Mode
Read DQM latency = 2
Read DQM latency = 1 for CL=1
M1
0
1
Driver Impedance
Z = 15 ohms (nom.)
Z = 30 ohms (nom.)
5
Rev. 2.1
Microchip MCU
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