350MHZ, CRYSTAL-TO-LVCMOS/LVTTL
FREQUENCY SYNTHESIZER
ICS8402I
Features
•
•
•
•
•
•
•
•
•
•
•
Two LVCMOS/LVTTL outputs
Selectable crystal oscillator interface or LVCMOS/LVTTL
TEST_CLK
Output frequency range: 15.625MHz to 350MHz
Crystal input frequency range: 12MHz to 40MHz
VCO range: 250MHz to 700MHz
Parallel or serial interface for programming counter and
output dividers
RMS period jitter: 30ps (maximum)
Cycle-to-cycle jitter: 100ps (maximum)
Full 3.3V or mixed 3.3V core/2.5V output supply
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
General Description
The ICS8402I is a general purpose,
Crystal-to-LVCMOS/LVTTL High Frequency
HiPerClockS™
Synthesizer and a member of the HiPerClockS™
family of High Performance Clock Solutions from
IDT. The ICS8402I has a selectable TEST_CLK or
crystal inputs. The VCO operates at a frequency range of 250MHz
to 700MHz. The VCO frequency is programmed in steps equal to
the value of the input reference or crystal frequency. The VCO and
output frequency can be programmed using the serial or parallel
interfaces to the configuration logic. The low phase noise
characteristics of the ICS8402I make it an ideal clock source for
Gigabit Ethernet and SONET applications.
ICS
Block Diagram
OE0
Pin Assignment
VCO_SEL
nP_LOAD
XTAL_IN
M4
M3
M2
M1
M0
OE1
VCO_SEL
XTAL_SEL
TEST_CLK
XTAL_IN
OSC
XTAL_OUT
1
0
M5
M6
M7
M8
N0
N1
nc
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
9 10 11 12 13 14 15 16
V
DD
OE1
OE0
Q1
Q0
TEST
XTAL_OUT
TEST_CLK
XTAL_SEL
V
DDA
S_LOAD
S_DATA
S_CLOCK
MR
PLL
PHASE DETECTOR
MR
÷
M
0
1
÷2
÷4
÷8
÷16
GND
VCO
Q0
Q1
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
CONFIGURATION
INTERFACE
LOGIC
TEST
ICS8402I
32 Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
32 Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
IDT™ / ICS™
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
1
ICS8402AYI REV. A OCTOBER 16, 2007
GND
V
DDO
ICS8402I
350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Functional Description
NOTE: The functional description that follows describes operation
using a 25MHz crystal. Valid PLL loop divider values for different
crystal or input frequencies are defined in the Input Frequency
Characteristics, Table 5, NOTE 1.
The ICS8402I features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth. A
fundamental crystal is used as the input to the on-chip oscillator.
The output of the oscillator is fed into the phase detector. A 25MHz
crystal provides a 25MHz phase detector reference frequency. The
VCO of the PLL operates over a range of 250MHz to 700MHz. The
output of the M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the
LVCMOS output buffers. The divider provides a 50% output duty
cycle.
The programmable features of the ICS8402I support two input
modes to program the M divider and N output divider. The two input
operational modes are parallel and serial.
Figure 1
shows the
timing diagram for each mode. In parallel mode, the nP_LOAD
input is initially LOW. The data on inputs M0 through M8 and N0
and N1 is passed directly to the M divider and N output divider. On
the LOW-to-HIGH transition of the nP_LOAD input, the data is
latched and the M divider remains loaded until the next LOW
transition on nP_LOAD or until a serial event occurs. As a result,
the M and N bits can be hardwired to set the M divider and N output
divider to a specific default state that will automatically occur
during power-up. The TEST output is LOW when operating in the
parallel input mode. The relationship between the VCO frequency,
the crystal frequency and the M divider is defined as follows:
fVCO = fXTAL x M
The M value and the required values of M0 through M8 are shown
in Table 3B, Programmable VCO Frequency Function Table. Valid
M values for which the PLL will achieve lock for a 25MHz reference
are defined as 10
≤
M
≤
28. The frequency out is defined as follows:
fout = fVCO = fXTAL x M
N
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is
LOW. The shift register is loaded by sampling the S_DATA bits with
the rising edge of S_CLOCK. The contents of the shift register are
loaded into the M divider and N output divider when S_LOAD
transitions from LOW-to-HIGH. The M divide and N output divide
values are latched on the HIGH-to-LOW transition of S_LOAD. If
S_LOAD is held HIGH, data at the S_DATA input is passed directly
to the M divider and N output divider on each rising edge of
S_CLOCK. The serial mode can be used to program the M and N
bits and test bits T1 and T0. The internal registers T0 and T1
determine the state of the TEST output as follows:
T1
0
0
1
1
T0
0
1
0
1
TEST Output
LOW
Shift Register Output
Output of M Divider
CMOS fOUT
S
ERIAL
L
OADING
S_CLOCK
S_DATA
t
T1
S
T0
H
*Null
N1
N0
M8
M7
M6 M5
M4
M3
M2
M1
M0
t
S_LOAD
nP_LOAD
t
S
P
ARALLEL
L
OADING
M0:M8, N0:N1
nP_LOAD
t
S
M, N
t
H
Time
*NOTE:
The NULL timing slot must be observed.
Figure 1. Parallel & Serial Load Operations
IDT™ / ICS™
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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ICS8402AYI REV. A OCTOBER 16, 2007
ICS8402I
350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Number
1
2, 3, 4, 28,
29, 30, 31, 32
5, 6
7
8, 16
9
10
11, 12
13
14, 15
Name
M5
M6, M7, M8, M0,
M1, M2, M3, M4
N0, N1
nc
GND
TEST
V
DD
OE1, OE0
V
DDO
Q1, Q0
Input
Input
Input
Unused
Power
Output
Power
Input
Power
Output
Pullup
Type
Pullup
Description
M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input.
Pulldown LVCMOS/LVTTL interface levels.
Pulldown Determines output divider value as defined in Table 3C, Function Table.
LVCMOS/LVTTL interface levels.
No connect.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels.
Core supply pin.
Output enable. When logic HIGH, the outputs are enabled (default).
When logic LOW, the outputs are in Tri-State. See Table 3D,
OE Function Table. LVCMOS / LVTTL interface levels.
Output supply pin.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers are reset
causing the outputs to go low. When Logic LOW, the internal dividers and the
Pulldown
outputs are enabled. Assertion of MR does not affect loaded M, N, and T
values. LVCMOS/LVTTL interface levels.
Pulldown
Pulldown
Pulldown
Clocks in serial data present at S_DATA input into the shift register on the
rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
LVCMOS/LVTTL interface levels.
Controls transition of data from shift register into the dividers.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Pullup
Selects between crystal oscillator or test inputs as the PLL reference source.
Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW.
LVCMOS/LVTTL interface levels.
17
MR
Input
18
19
20
21
22
23
24,
25
26
S_CLOCK
S_DATA
S_LOAD
V
DDA
XTAL_SEL
TEST_CLK
XTAL_OUT
XTAL_IN
nP_LOAD
Input
Input
Input
Power
Input
Input
Input
Pulldown Test clock input. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Parallel load input. Determines when data present at M8:M0 is loaded into M
Pulldown divider, and when data present at N1:N0 sets the N output divider value.
LVCMOS/LVTTL interface levels.
Pullup
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS/LVTTL interface levels.
Input
27
VCO_SEL
Input
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
IDT™ / ICS™
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
3
ICS8402AYI REV. A OCTOBER 16, 2007
ICS8402I
350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
V
DD
, V
DDO
= 3.465V
V
DD
= 3.465V, V
DDO
= 2.625V
Test Conditions
Minimum
Typical
4
13
11
51
51
V
DDO
= 3.465V
V
DDO
= 2.625V
5
7
7
12
Maximum
Units
pF
pF
pF
k
Ω
k
Ω
R
PULLDOWN
Input Pulldown Resistor
R
OUT
Output Impedance
Ω
Ω
Function Tables
Table 3A. Parallel and Serial Mode Function Table
Inputs
MR
H
L
L
L
L
L
L
L
nP_LOAD
X
L
↑
H
H
H
H
H
M
X
Data
Data
X
X
X
X
X
N
X
Data
Data
X
X
X
X
X
S_LOAD
X
X
L
L
↑
↓
L
H
S_CLOCK
X
X
X
↑
L
L
X
↑
S_DATA
X
X
X
Data
Data
Data
X
Data
Conditions
Reset. Forces outputs LOW.
Data on M and N inputs passed directly to the M divider
and N output divider. TEST output forced LOW.
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
NOTE: L = LOW
H = HIGH
X = Don’t care
↑
= Rising edge transition
↓
= Falling edge transition
IDT™ / ICS™
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
4
ICS8402AYI REV. A OCTOBER 16, 2007
ICS8402I
350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Table 3B. Programmable VCO Frequency Function Table
VCO Frequency
(MHz)
250
275
•
•
650
675
700
256
M Divide
10
11
•
•
26
27
28
M8
0
0
•
•
0
0
0
128
M7
0
0
•
•
0
0
0
64
M6
0
0
•
•
0
0
0
32
M5
0
0
•
•
0
0
0
16
M4
0
0
•
•
1
1
1
8
M3
1
1
•
•
1
1
1
4
M2
0
0
•
•
0
0
1
2
M1
1
1
•
•
1
1
0
1
M0
0
1
•
•
0
1
0
NOTE 1: These M divide values and the resulting frequencies correspond to a TEST_CLK or crystal frequency of 25MHz.
Table 3C. Programmable Output DividerFunction Table
Inputs
N1
0
0
1
1
N0
0
1
0
1
N Divider Value
2
4
8
16
Output Frequency (MHz)
Minimum
125
62.5
31.25
15.625
Maximum
350
175
87.5
43.75
Table 3D. OE Function Table
Inputs
OE0
0
0
1
1
OE1
0
1
0
1
Q0
Hi-Z
Hi-Z
Enabled
Enabled
Output
Q1
Hi-Z
Enabled
Hi-Z
Enabled
IDT™ / ICS™
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
5
ICS8402AYI REV. A OCTOBER 16, 2007
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