Data Sheet
November 2016
5- or 10-Output Any-to-Any Clock Multipliers
General Description
The MAX24405 and MAX24410 are flexible, high-
performance clock multiplier/synthesizer ICs with two
independent APLLs. Each APLL performs any-to-any
frequency conversion. From any input clock frequency
9.72MHz to 750MHz these devices can produce
frequency-locked APLL output frequencies up to
750MHz and as many as 10 differential output clock
signals that are integer divisors of the APLL
frequencies. Output jitter is typically 0.18 to 0.3ps RMS
for an integer multiply and 0.25 to 0.4ps RMS for a
fractional multiply (12kHz to 20MHz). Each device can
configure itself from an external EEPROM so that clock
signals are available immediately after power-up or
reset.
MAX24405, MAX24410
Features
Input Clocks
One Crystal or CMOS Input
Three Differential or CMOS Inputs
Differential to 750MHz, CMOS to 160MHz
Clock Selection By Pin or Register Control
APLLs Perform High Resolution Fractional-N
Clock Multiplication
Any Output Frequency from <1Hz to 750MHz
Each Output Has an Independent Divider
Output Jitter Typically 0.18 to 0.3ps RMS for
Integer Multiply and 0.25 to 0.4ps RMS for
Fractional Multiply (12kHz to 20MHz)
Outputs are CML or 2xCMOS, Can Interface to
LVDS, LVPECL, HSTL, SSTL and HCSL
CMOS Output Voltage from 1.5V to 3.3V
Automatic Self-Configuration at Power-Up
from External EEPROM Memory
SPI™ Processor Interface
1.8V + 3.3V Operation (5V Tolerant)
-40 to +85
C
Operating Temp. Range
Two APLLs Plus 5 or 10 Output Clocks
Applications
Frequency conversion and synthesis applications in a
wide variety of equipment types
Ordering Information
PART
MAX24405EXG+
MAX24410EXG+
OUTPUTS
5
10
TEMP
RANGE
-40 to +85
-40 to +85
PIN-
PACKAGE
81-CSBGA
81-CSBGA
General Features
+Denotes
a lead(Pb)-free/RoHS-compliant package.
Register Map appears on page
18.
Block Diagram
APLL1
3.7-4.2GHz,
Sub-ps jitter,
Fractional-N
A
DIV1
DIV2
DIV3
DIV4
DIV5
DIV6
DIV7
DIV8
DIV9
DIV10
OC1POS/NEG
OC2POS/NEG
OC3POS/NEG
OC4POS/NEG
OC5POS/NEG
OC6POS/NEG
OC7POS/NEG
OC8POS/NEG
OC9POS/NEG
OC10POS/NEG
B
Figure 4-2
IC1POS/NEG
IC2POS/NEG
IC3POS/NEG
XIN
XOUT
APLL2
XO
3.7-4.2GHz,
Sub-ps jitter,
Fractional-N
C
MAX24410 only
MAX24410 only
D
Processor SPI Port
EEPROM SPI Port
and HW Control and Status Pins
JTAG
RST_N
TEST
INTREQ
GPIO1
GPIO2
AC / GPIO3
SS / GPIO4
JTRST_N
JTMS
JTCLK
JTDI
JTDO
CS_N
SCLK
SDI
SDO
ECS_N
ESCLK
ESDI
ESDO
1
MAX24405, MAX24410
Table of Contents
1.
2.
2.1
2.2
2.3
3.
4.
4.1
4.2
4.3
4.4
4.5
APPLICATION EXAMPLES .......................................................................................................... 4
DETAILED FEATURES ................................................................................................................. 5
APLL F
EATURES
.......................................................................................................................... 5
O
UTPUT
C
LOCK
F
EATURES
........................................................................................................... 5
G
ENERAL
F
EATURES
.................................................................................................................... 5
PIN DESCRIPTIONS ..................................................................................................................... 6
FUNCTIONAL DESCRIPTION ...................................................................................................... 9
D
EVICE
I
DENTIFICATION AND
P
ROTECTION
..................................................................................... 9
L
OCAL
O
SCILLATOR OR
C
RYSTAL
.................................................................................................. 9
External Oscillator ...................................................................................................................................9
On-Chip Crystal Oscillator ......................................................................................................................9
4.2.1
4.2.2
I
NPUT
S
IGNAL
F
ORMAT
C
ONFIGURATION
.......................................................................................10
APLL C
ONFIGURATION
................................................................................................................11
Input Selection and Frequency ............................................................................................................ 11
Output Frequency ................................................................................................................................ 11
Enable, Signal Format, Voltage and Interfacing .................................................................................. 12
Frequency Configuration ...................................................................................................................... 13
Phase Adjustment ................................................................................................................................ 13
4.4.1
4.4.2
4.5.1
4.5.2
4.5.3
O
UTPUT
C
LOCK
C
ONFIGURATION
.................................................................................................12
4.6
4.7
4.8
4.9
5.
5.1
M
ICROPROCESSOR
I
NTERFACE
....................................................................................................14
R
ESET
L
OGIC
..............................................................................................................................16
P
OWER
-S
UPPLY
C
ONSIDERATIONS
...............................................................................................16
I
NITIALIZATION AND
EEPROM C
ONFIGURATION
M
EMORY
..............................................................16
REGISTER DESCRIPTIONS ........................................................................................................17
R
EGISTER
T
YPES
........................................................................................................................17
Status Bits ............................................................................................................................................ 17
Configuration Fields ............................................................................................................................. 17
Bank-Switched Registers ..................................................................................................................... 17
5.1.1
5.1.2
5.1.3
5.2
5.3
R
EGISTER
M
AP
...........................................................................................................................18
R
EGISTER
D
EFINITIONS
...............................................................................................................19
Global Registers................................................................................................................................... 19
GPIO Registers .................................................................................................................................... 24
APLL Registers .................................................................................................................................... 27
Output Clock Registers ........................................................................................................................ 33
5.3.1
5.3.2
5.3.3
5.3.4
6.
6.1
6.2
6.3
6.4
7.
8.
8.1
8.2
9.
9.1
9.2
JTAG AND BOUNDARY SCAN ...................................................................................................37
JTAG D
ESCRIPTION
....................................................................................................................37
JTAG TAP C
ONTROLLER
S
TATE
M
ACHINE
D
ESCRIPTION
..............................................................38
JTAG I
NSTRUCTION
R
EGISTER AND
I
NSTRUCTIONS
.......................................................................40
JTAG T
EST
R
EGISTERS
...............................................................................................................41
ELECTRICAL CHARACTERISTICS ............................................................................................42
PIN ASSIGNMENTS.....................................................................................................................51
MAX24405 P
IN
A
SSSIGNMENT
....................................................................................................51
MAX24410 P
IN
A
SSSIGNMENT
....................................................................................................53
PACKAGE AND THERMAL INFORMATION ...............................................................................55
P
ACKAGE
T
OP
M
ARK
F
ORMAT
......................................................................................................55
T
HERMAL
S
PECIFICATIONS
...........................................................................................................56
2
MAX24405, MAX24410
10.
11.
ACRONYMS AND ABBREVIATIONS ..........................................................................................57
DATA SHEET REVISION HISTORY ........................................................................................... 58
List of Figures
Figure 1-1. Frequency Synthesis Application Example ................................................................................................4
Figure 1-2. Frequency Conversion Application Example .............................................................................................4
Figure 4-1. Crystal Equivalent Circuit / Crystal and Capacitor Connections ............................................................. 10
Figure 4-2. APLL Block Diagram ............................................................................................................................... 11
Figure 4-3. SPI Read Transaction Functional Timing................................................................................................ 15
Figure 4-4. SPI Write Enable Transaction Functional Timing ................................................................................... 15
Figure 4-5. SPI Write Transaction Functional Timing ................................................................................................ 15
Figure 6-1. JTAG Block Diagram ............................................................................................................................... 37
Figure 6-2. JTAG TAP Controller State Machine ...................................................................................................... 39
Figure 7-1. Recommended External Components for Interfacing to Differential Inputs ............................................ 44
Figure 7-2. Recommended External Components for Interfacing to CML Outputs ................................................... 46
Figure 7-3. Recommended Confguration for Interfacing to HCSL Components ....................................................... 47
Figure 7-4. SPI Interface Timing Diagram ................................................................................................................. 49
Figure 7-5. JTAG Timing Diagram ............................................................................................................................. 50
Figure 8-1. MAX24405 Pin Assignment Diagram ...................................................................................................... 52
Figure 8-2. MAX24410 Pin Assignment Diagram ...................................................................................................... 54
Figure 9-1. Device Top Mark ..................................................................................................................................... 55
List of Tables
Table 3-1. Input Clock Pin Descriptions .......................................................................................................................6
Table 3-2. Output Clock Pin Descriptions .....................................................................................................................6
Table 3-3. Global Pin Descriptions ...............................................................................................................................6
Table 3-4. SPI Interface Pin Descriptions .....................................................................................................................7
Table 3-5. External EEPROM SPI Interface Pin Descriptions ......................................................................................7
Table 3-6. JTAG Interface Pin Descriptions .................................................................................................................7
Table 3-7. Power-Supply Pin Descriptions ...................................................................................................................7
Table 4-1. Crystal Selection Parameters ................................................................................................................... 10
Table 4-2. Input Clock Capabilities ............................................................................................................................ 11
Table 5-1. Register Map ............................................................................................................................................ 18
Table 6-1. JTAG Instruction Codes ........................................................................................................................... 40
Table 6-2. JTAG ID Code .......................................................................................................................................... 41
Table 7-1. Recommended DC Operating Conditions ................................................................................................ 42
Table 7-2. Electrical Characteristics: Supply Currents .............................................................................................. 42
Table 7-3. Electrical Characteristics: Non-Clock CMOS/TTL Pins ............................................................................ 43
Table 7-4. Electrical Characteristics: Clock Inputs .................................................................................................... 44
Table 7-5. Electrical Characteristics: CML Clock Outputs ......................................................................................... 45
Table 7-6. Electrical Characteristics: CMOS and HSTL (Class I) Clock Outputs ...................................................... 46
Table 7-7. Electrical Characteristics: Clock Output Timing ....................................................................................... 47
Table 7-8. Electrical Characteristics: Jitter Specifications ......................................................................................... 47
Table 7-9. Electrical Characteristics: Typical Output Jitter Performance .................................................................. 47
Table 7-10. Electrical Characteristics: Typical Input-to-Output Clock Delay ............................................................. 48
Table 7-11. Electrical Characteristics: Typical Output-to-Output Clock Delay .......................................................... 48
Table 7-12. Electrical Characteristics: SPI Interface Timing ..................................................................................... 49
Table 7-13. Electrical Characteristics: External EEPROM SPI Interface Timing ...................................................... 49
Table 7-14. Electrical Characteristics: JTAG Interface Timing .................................................................................. 50
Table 8-1. MAX24405 Pin Assignments Sorted by Signal Name .............................................................................. 51
Table 8-2. MAX24410 Pin Assignments Sorted by Signal Name .............................................................................. 53
Table 9-1. Package Top Mark Legend ...................................................................................................................... 55
Table 9-2. CSBGA Package Thermal Properties ...................................................................................................... 56
3
MAX24405, MAX24410
1. Application Examples
Figure 1-1. Frequency Synthesis Application Example
MAX24410
50MHz
XO
APLL1
25MHz
125MHz
125MHz
156.25MHz
156.25MHz
133MHz
200MHz
100MHz
66MHz
33MHz
Combination of 25MHz, 125MHz and
156.25MHz Ethernet frequencies
-plus-
Multiples of 33MHz and 100MHz for
processor and memory clocks
Any combination of differential or
2x single-ended signal format
APLL2
Figure 1-2. Frequency Conversion Application Example
MAX24410
APLL1
19.44MHz
Reference Clock
APLL2
25MHz
125MHz
125MHz
156.25MHz
156.25MHz
155.52MHz
155.52MHz
77.76MHz
622.08MHz
622.08MHz
Synchronous Ethernet Clocks:
any combination of 25M, 125M,
156.25M and related frequencies
SDH/SONET Clocks: Nx6.48MHz
to 622.08MHz
Any combination of differential or
2x single-ended signal format
4
MAX24405, MAX24410
2. Detailed Features
2.1
APLL Features
Two independent APLLs
Very high-resolution fractional scaling (i.e. non-integer multiplication)
Output jitter is typically
0.18 to 0.3ps RMS for an integer multiply and 0.25 to 0.4ps RMS for a fractional multiply
(12kHz to 20MHz integration band, for output frequencies >100MHz)
Telecom output frequencies include 622.08MHz for SONET/SDH and 625MHz for Synchronous Ethernet
Bypass mode for each APLL supports system testing and allows the devices to be used in fanout
applications
2.2
Output Clock Features
Up to five (MAX24405) or ten (MAX24410) low-jitter output clocks
Each output can be one differential output or two CMOS/TTL outputs
Outputs easily interface with CML, LVDS, LVPECL, HSTL, SSTL, HCSL components
Each output can be any integer divisor of an APLL output clock
Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTN
Can produce clock frequencies for microprocessors, ASICs, FPGAs and other components
Can produce PCIe-compliant output clocks (PCIe gen. 1, 2 and 3)
Per-output delay adjustment
Per-output enable/disable
2.3
General Features
SPI serial microprocessor interface
Optional automatic self-configuration at power-up from external EEPROM memory
Four general-purpose I/O pins
Register set can be write-protected
5
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