UT1553 BCRTM
F
EATURES
p
Comprehensive MIL-STD-1553 dual-redundant Bus
p
p
p
p
p
Controller (BC) and Remote Terminal (RT) and
Monitor (M) functions
MIL-STD-1773 compatible
Multiple message processing capability in BC
Time tagging and message logging in RT and M modes
Automatic polling and intermessage delay in
BC mode
Programmable interrupt scheme and internally
generated interrupt history list
p
Register-oriented architecture to enhance
programmability
p
DMA memory interface with 64K addressability
p
Internal self-test
p
Radiation-hardened option available for 84-lead
flatpack package only
p
Remote terminal operations in ASD/ENASD-certified
(SEAFAC)
p
Available in 84-pin pingrid array, 84-lead flatpack, 84-
lead leadless chip-carrier
p
Standard Microcircuit Drawing 5962-89577 available
- QML Q and V compliant
REGISTERS
CONTROL
HIGH-PRIORITY
STD PRIORITY LEVEL
STD PRIORITY PULSE
STATUS
CURRENT BC (or M) BLOCK/
RT DESCRIPTOR SPACE
POLLING COMPARE
CLOCK &
RESET
LOGIC
INTERRUPT
HANDLER
BC PROTOCOL
&
MESSAGE
HANDLER
BUILT-IN-TEST WORD
CURRENT COMMAND
INTERRUPT LOG
LIST POINTER
HIGH-PRIORITY
INTERRUPT ENABLE
16
HIGH-PRIORITY
INTERRUPT STATUS
STANDARD INTERRUPT
ENABLE
16
RT/MONITOR
PROTOCOL &
MESSAGE
HANDLER
BUILT-
IN-
TEST
16
RT ADDRESS
BUILT-IN-TEST
START COMMAND
RESET COMMAND
RT TIMER
RESET COMMAND
MONITOR ADDRESS
CONTROL
MONITOR ADDRESS
SELECT (0-15)
ADDRESS
MONITOR ADDRESS
SELECT (16-31)
16
16
DATA
12MHz
MASTER
RESET
1553
DATA
CHANNEL
A
1553
DATA
CHANNEL
B
DUAL
CHANNEL
ENCODER/
DECODER
MODULE
PARALLEL-
TO-SERIAL
CONVER-
SION
16
BUS
TRANSFER
LOGIC
SERIAL-TO-
PARALLEL
CONVER-
SION
TIMERON
TIMEOUT
ADDRESS
GENERATOR
16
DMA/CPU
CONTROL
16
DMA ARBITRATION
REGISTER CONTROL
DUAL-PORT MEMORY CONTROL
Figure 1. BCRTM Block Diagram
BCRTM-1
Table of Contents
1.0
INTRODUCTION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
1.2
1.3
2.0
3.0
4.0
5.0
Features - Remote Terminal (RT) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Features - Bus Controller (BC) Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Features - Monitor (M) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
PIN IDENTIFICATION AND DESCRIPTION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
INTERNAL REGISTERS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SYSTEM OVERVIEW
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SYSTEM INTERFACE.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1
5.2
5.3
5.4
5.6
6.0
DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Hardware Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
CPU Interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
RAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Transmitter/Receiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
RT Functional Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
6.1.1 RT Subaddress Descriptor Definitions . . . . . . . . . . . . . . . . . . . . . . . . . .24
6.1.2 Message Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
6.1.3 Mode Code Descriptor Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
RT Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
RT Operational Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
BC Functional Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
BC Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
BC Operational Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
BC Operational Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Monitor Functional Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Monitor Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Monitor Operational Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
REMOTE TERMINAL ARCHITECTURE.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1
6.2
6.3
7.0
BUS CONTROLLER ARCHITECTURE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1
7.2
7.3
7.4
7.5
8.0
MONITOR ARCHITECTURE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.1
8.2
8.3
9.0
10.0
11.0
12.0
13.0
EXCEPTION HANDLING AND INTERRUPT LOGGING
. . . . . . . . . . . . . . . . . . . . . . . . 36
MAXIMUM AND RECOMMENDED OPERATING CONDITIONS
. . . . . . . . . . . . . . . . 40
DC ELECTRICAL CHARACTERISTICS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
AC ELECTRICAL CHARACTERISTICS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
PACKAGE OUTLINE DRAWINGS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
BCRTM-2
1.0 I
NTRODUCTION
The monolithic CMOS UT1553 BCRTM provides the
system designer with an intelligent solution to
MIL-STD-1553B multiplexed serial data bus design
problems. The UT1553B BCRTM is a single-chip device
that implements all three of defined MIL-STD-1553B
functions - Bus Controller, Remote Terminal, and Monitor.
Designed to reduce host CPU overhead, the BCRTM’s
powerful state machines automatically execute message
transfers, provide interrupts, and generate status
information. Multiple registers offer many programmable
functions as well as extensive information for host use. In
the BC mode, the BCRTM uses a linked-list message
scheme to provide the host with message chaining
capability. The BCRTM enhances memory use by
supporting variable-size, relocatable data blocks. In the RT
mode, the BCRTM implements time-tagging and message
history functions. It also supports multiple (up to 128)
message buffering and variable length messages to any
subaddress.In the Monitor (M) mode, the BCRTM’s
powerful linked list command block structure allows it to
process a series of monitored 1553 messages without the
intervention of the host. The BCRTM can store as much bus
traffic as can be contained in its 64K memory space. In
addition, the host has the capability of instructing the
BCRTM to monitor and store data for only selected remote
terminals.
The UT1553 BCRTM is an intelligent, versatile, and easy
to implement device -- a powerful asset to system designers.
1.1 Features - Remote Terminal (RT) Mode
Indexing
The BCRTM is programmable to index or buffer messages
on a subaddress-by-subaddress basis. The BCRTM, which
can index as many as 128 messages, can also assert an
interrupt when either the selected number of messages is
reached or every time a specified subaddress is accessed.
Variable Space Allocation
The BCRTM can use as little or as much memory (up to
64K) as needed.
Selectable Data Storage
Address programmability within the BCRTM provides
flexible data placement and convenient access.
Sequential Data Storage
The BCRTM stores/retrieves, by subaddress, all messages
in the order in which they are transacted.
Sequential Message Status Information
The BCRTM provides message validity, time-tag, and
word-count information, and stores it sequentially in a
separate, cross-referenced list.
Illegalizing Mode Codes and Subaddresses
The host can declare mode codes and subaddresses illegal
by setting the appropriate bit(s) in memory.
Programmable Interrupt Selection
The host CPU can select various events to cause an interrupt
with provision for high and standard priority interrupts.
Interrupt History List
The BCRTM provides an Interrupt History List that records,
in the order of occurrence, the events that caused the
interrupts. The list length is programmable.
1.2 Features - Bus Controller (BC) Mode
Multiple Message Processing
The BCRTM autonomously processes any number of
messages or lists of messages that may be stored in a 64K
memory space.
Automatic Intermessage Delay
When programmed by the host, the BCRTM can delay a
host-specified time before executing the next message in
sequence.
Automatic Polling
When polling, the BCRTM interrogates the remote
terminals and then compares their status word responses to
the contents of the Polling Compare Register. The BCRTM
can interrupt the host CPU if an erroneous remote terminal
status word response occurs.
Automatic Retry
The BCRTM can automatically retry a message on busy,
message error, and/or response time-out conditions. The
BCRTM can retry up to four times on the same or on the
alternate bus.
Programmable Interrupt Selection
The host CPU can select various events to cause an interrupt
with provision for high and standard priority interrupts.
Interrupt History List
The BCRTM provides an Interrupt History List that records,
in the order of occurrence, the events that caused the
interrupts. The list length is programmable.
Variable Space Allocation
The BCRTM uses as little or as much memory (up to 64K)
as needed.
Selectable Data Storage
Address programmability within the BCRTM provides
flexible data placement and convenient access.
BCRTM-3
1.3 Features - Monitor (M) Mode
Command History List
The BCRTM’s linked list command block structure permits
the BCRTM to process a series of monitored messages
without host intervention.
Monitor Selected Terminal Address
The host can select the remote terminals to be monitored by
programming the proper bits in the Terminal Address Select
registers (Registers16 and 17). The BCRTM can monitor
any or all remote terminals.
Variable Space Allocation
The BCRTM can use as little or as much memory (up to
64K) as needed
Selectable Data Storage
Address programmability within the BCRTM provides
flexible data placement and convenient access.
Sequential Data Storage
The BCRTM stores, by Terminal Address, all 1553
messages in the order in which they are transacted.
Programmable Interrupt Selection
The host can select a wide variety of events that may cause
an interrupting event.
Interrupt History List
The BCRTM stores, chronologically in memory, an
Interrupt History List of each event that causes an interrupt.
BCRTM-4
2.0 P
IN
I
DENTIFICATION
A
ND
D
ESCRIPTION
TAZ
TAO
TBZ
TBO
RAZ
RAO
RBZ
RBO
RTA0
RTA1
RTA2
RTA3
RTA4
RTPTY
STDINTL
STDINTP
HPINT
TIMERON
COMSTR
SSYSF
BCRTF
CHA/B
TEST
DMAR
DMAG
DMAGO
DMACK
BURST
TSCTL
13
14
17
18
15
16
19
20
28
29
30
31
32
33
68
69
70
25
27
72
75
26
73
56
57
67
58
74
55
(K3)
(L2)
(L4)
(K6)
(L3)
(K4)
(K5)
(L5)
(K8) **
(L9) **
(L10) **
(K9) **
(L11) **
(K10) **
(A6) +
(A4)
(B4) +
(K7)
(L8)
(A2)
(B2)
(J7)
(B3)*
(A10) +
(A9)
(B5)
(B8) +
(A1)
(B9)
(J10)
(K11)
(J11)
(H10)
(H11)
(G9)
(G10)
(G11)
(E9)
(E11)
(E10)
(F11)
(D11)
(D10)
(C11)
(B11)
(K1)
(J1)
(H2)
(H1)
(G3)
(G2)
(G1)
(F1)
(E1)
(E2)
(F2)
(D1)
(D2)
(C1)
(B1)
(C2)
(L6)
(F9)
(C6)
(E3)
(F3)
(J6)
(F10)
(B6)
(J5)
(C5)
(A3)
34
35
36
37
38
39
40
41
44
45
46
47
48
49
50
51
9
8
7
6
5
4
3
2
83
82
81
80
79
78
77
76
23
43
64
84
1
22
42
63
21
65
71
A0 ++
A1 ++
A2 ++
A3 ++
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
V
SS
V
SS
CLK
MCLK
MCLKD2
BIPHASE OUT
BIPHASE IN
ADDRESS+
LINES
TERMINAL
ADDRESS
STATUS
SIGNALS
DATA
++
LINES
DMA
SIGNALS
RD
WR
CS
AEN
BCRTSEL
LOCK
CONTROL
MRST
SIGNALS
EXTOVR
RRD
RWR
MEMCSI
MEMCSO
**
+
++
*
Pin internally pulled up.
Pin at high impedance when not asserted
Bidirectional pin.
Formerly MEMWIN.
61
60
62
66
11
12
10
24
53
52
59
54
(B7)
(C7)
(A7)
(A5)
(L1) * *
(K2) * *
(J2)
(L7) * *
(A11)
(C10)
(A8) * *
(B10)
POWER
GROUND
CLOCK
SIGNALS
() Pingrid array pin identification in parentheses.
LCC, flatpack pin number not in parentheses.
Figure 2. BCRT Functional Pin Description
BCRTM-5
FPGA/CPLD
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