S i 5 9 0 / 5 91
1 ps M
AX
J
I T T E R
C
RYSTAL
O
SC ILLA TOR
(XO)
(10 M H
Z TO
525 MH
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 525 MHz
3rd generation DSPLL
®
with superior
jitter performance: 1 ps max jitter
Better frequency stability than SAW-
based oscillators
Internal fundamental mode crystal
ensures high reliability
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
–40 to +85 ºC operating
temperature range
Si5602
Applications
Ordering Information:
See page 6.
SONET/SDH (OC-3/12/48)
Networking
SD/HD SDI/3G SDI video
Test and measurement
Storage
FPGA/ASIC clock generation
Description
The Si590/591 XO utilizes Silicon Laboratories’ advanced DSPLL
®
circuitry
to provide a low jitter clock at high frequencies. The Si590/591 is available
with any-rate output frequency from 10 to 525 MHz. Unlike a traditional XO,
where a unique crystal is required for each output frequency, the Si590/591
uses one fixed crystal to provide a wide range of output frequencies. This IC
based approach allows the crystal resonator to provide exceptional
frequency stability and reliability. In addition, DSPLL clock synthesis provides
superior supply noise rejection, simplifying the task of generating low jitter
clocks in noisy environments typically found in communication systems. The
Si590/591 IC based XO is factory configurable for a wide variety of user
specifications including frequency, supply voltage, output format, and
temperature stability. Specific configurations are factory programmed at time
of shipment, thereby eliminating long lead times associated with custom
oscillators.
Pin Assignments:
See page 5.
(Top View)
NC
1
6
V
DD
OE
2
5
CLK–
GND
3
4
CLK+
Si590 (LVDS/LVPECL/CML)
OE
1
6
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
2
5
NC
GND
3
4
CLK
Si590 (CMOS)
17 k
*
Any-rate
10–525 MHz
DSPLL
®
Clock
Synthesis
OE
1
6
V
DD
OE
Fixed
Frequency
XO
NC
2
5
CLK–
17 k
*
GND
3
4
CLK+
Si591 (LVDS/LVPECL/CML)
GND
*Note: Output Enable High/Low Options Available – See Ordering Information
Preliminary Rev. 0.25 7/09
Copyright © 2009 by Silicon Laboratories
Si590/591
Si590/591
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Supply Voltage
1
Symbol
V
DD
Test Condition
3.3 V option
2.5 V option
1.8 V option
Supply Current
I
DD
Output enabled
LVPECL
CML
LVDS
CMOS
Tristate mode
Output Enable (OE)
2
Operating Temperature Range
T
A
V
IH
V
IL
Min
2.97
2.25
1.71
—
—
—
—
—
0.75 x V
DD
—
–40
Typ
3.3
2.5
1.8
110
100
90
80
60
—
—
—
Max
3.63
2.75
1.89
125
110
100
90
75
—
0.5
85
V
ºC
V
Units
mA
Notes:
1.
Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 6 for further details.
2.
OE pin includes an internal 17 k pullup resistor to V
DD
for output enable active high or a 17 k pull-down resistor to
GND for output enable active low. See 3. "Ordering Information" on page 6.
Table 2. CLK± Output Frequency Characteristics
Parameter
Nominal Frequency
1,2
Initial Accuracy
Symbol
f
O
Test Condition
LVPECL/LVDS/CML
CMOS
Measured at +25 °C at time of
shipping
Note 3, second option code “C”
Note 4, second option code “B”
Note 4, second option code “A”
second option code “C”
Min
10
10
—
—
—
—
—
—
—
—
Typ
—
—
±1.5
—
—
—
—
—
—
—
Max
525
160
—
±30
±50
±100
±20
±25
±50
10
Units
MHz
ppm
ppm
ppm
ppm
ppm
ppm
ppm
ms
f
i
Total Stability
Temperature Stability
Powerup Time
5
second option code “B”
second option code “A”
t
OSC
Notes:
1.
See Section 3. "Ordering Information" on page 6 for further details.
2.
Specified at time of order by part number.
3.
Includes initial accuracy, temperature, shock, vibration, power supply and load drift, and 10 years aging at 40 °C. See
3. "Ordering Information" on page 6.
4.
Includes initial accuracy, temperature, shock, vibration, power supply and load drift, and 15 years aging at 70 °C. See
3. "Ordering Information" on page 6.
5.
Time from powerup or tristate mode to f
O
.
2
Preliminary Rev. 0.25
Si590/591
Table 3. CLK± Output Levels and Symmetry
Parameter
LVPECL Output Option
1
Symbol
V
O
V
OD
V
SE
Test Condition
mid-level
swing (diff)
swing (single-ended)
mid-level
swing (diff)
Min
V
DD
– 1.42
1.1
0.55
1.125
0.5
Typ
—
Max
V
DD
– 1.25
1.9
0.95
1.275
0.9
Units
V
V
PP
V
PP
V
V
PP
—
—
1.20
0.7
LVDS Output Option
2
V
O
V
OD
CML Output Option
2
V
O
V
OD
mid-level
swing
(diff)
—
0.70
0.8 x V
DD
V
DD
– 0.75
0.95
—
—
—
2
—
—
1.20
V
DD
V
V
PP
V
CMOS Output Option
3
V
OH
V
OL
—
LVPECL/LVDS/CML
CMOS with C
L
= 15 pF
—
—
45
0.4
350
—
55
ps
ns
%
Rise/Fall time (20/80%)
t
R,
t
F
Symmetry (duty cycle)
SYM
LVPECL:
LVDS:
CMOS:
V
DD
– 1.3 V (diff)
1.25 V (diff)
V
DD
/2
Notes:
1.
50
to V
DD
– 2.0 V.
2.
R
term
= 100
(differential).
3.
C
L
= 15 pF. Sinking or sourcing 12 mA for V
DD
= 3.3 V, 6 mA for V
DD
= 2.5 V, 3 mA for V
DD
= 1.8 V.
Table 4. CLK± Output Phase Jitter
Parameter
Phase Jitter (RMS)
1
for 50 MHz < F
OUT
< 525 MHz
(LVPECL/LVDS/CML)
Phase Jitter (RMS)
2
for 50 MHz < F
OUT
< 160 MHz
(CMOS)
Symbol
Test Condition
12 kHz to 20 MHz
Min
—
Typ
0.5
Max
1.0
Units
ps
J
J
12 kHz to 20 MHz
—
0.6
1.0
ps
Notes:
1.
Differential Modes LVPECL/LVDS/CML. 3.3 and 2.5 V supply voltage options only.
2.
Single-ended CMOS output phase jitter measured using 33
series termination into 50
phase noise test equipment.
3.3 V supply voltage option only.
Table 5. CLK± Output Period Jitter
Parameter
Period Jitter*
Symbol
J
PER
Test Condition
RMS
Peak-to-Peak
Min
—
—
Typ
—
—
Max
3
35
Units
ps
*Note:
Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.
Preliminary Rev. 0.25
3
Si590/591
Table 6. Absolute Maximum Ratings
1
Parameter
Maximum Operating Temperature
Supply Voltage, 1.8 V Option
Supply Voltage, 2.5/3.3 V Option
Input Voltage (any input pin)
Storage Temperature
ESD Sensitivity (HBM, per JESD22-A114)
Soldering Temperature (Pb-free profile)
2
Soldering Temperature Time @ T
PEAK
(Pb-free profile)
2
Symbol
T
AMAX
V
DD
V
DD
V
I
T
S
ESD
T
PEAK
t
P
Rating
85
–0.5 to +1.9
–0.5 to +3.8
–0.5 to V
DD
+ 0.3
–55 to +125
2500
260
20–40
Units
ºC
V
V
Volts
ºC
V
ºC
seconds
Notes:
1.
Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2.
The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at
www.silabs.com/VCXO
for further information, including soldering profiles.
Table 7. Environmental Compliance
The Si590/591 meets the following qualification test requirements.
Parameter
Mechanical Shock
Mechanical Vibration
Solderability
Gross & Fine Leak
Resistance to Solvents
Conditions/Test Method
MIL-STD-883G, Method 2002.3 B
MIL-STD-883G, Method 2007.3 A
MIL-STD-883G, Method 203.8
MIL-STD-883G, Method 1014.7
MIL-STD-883G, Method 2015
4
Preliminary Rev. 0.25
Si590/591
2. Pin Descriptions
(Top View)
NC
1
6
V
DD
OE
1
6
V
DD
OE
1
6
V
DD
OE
2
5
CLK–
NC
2
5
NC
NC
2
5
CLK–
GND
3
4
CLK+
GND
3
4
CLK
GND
3
4
CLK+
Si590
LVDS/LVPECL/CML
Si590
CMOS
Si591
LVDS/LVPECL/CML
Table 8. Pinout for Si590 Series
Pin
1
2
3
4
5
6
Symbol
OE*
OE*
GND
CLK+
CLK–
V
DD
LVDS/LVPECL/CML Function
No connection
Make no external connection to this pin
Output enable
Electrical and Case Ground
Oscillator Output
Complementary Output
Power Supply Voltage
CMOS Function
Output enable
No connection
Make no external connection to this pin
Electrical and Case Ground
Oscillator Output
No connection
Make no external connection to this pin
Power Supply Voltage
*Note:
OE pin includes an internal 17 k pullup resistor to V
DD
for output enable active high or a 17 k pulldown resistor to
GND for output enable active low. See 3. "Ordering Information" on page 6.
Table 9. Pinout for Si591 Series
Pin
1
2
3
4
5
6
Symbol
OE*
No connection
Make no external connection to this pin
GND
CLK+
CLK–
V
DD
LVDS/LVPECL/CML Function
Output enable
No connection
Make no external connection to this pin
Electrical and Case Ground
Oscillator Output
Complementary output
Power Supply Voltage
*Note:
OE pin includes an internal 17 k pullup resistor to V
DD
for output enable active high or a 17 k pulldown resistor to
GND for output enable active low. See 3. "Ordering Information" on page 6.
Preliminary Rev. 0.25
5
FPGA/CPLD
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