PF947-01
SRM20W117LLTT/SLTT
2/7
Vol
ow
rL
upe ration
S e ts
Op oduc
Pr
tag
e
1M-Bit Static RAM
q
Super Low Voltage Operation and Low Current Consumption
q
Access Time 120ns (1.8V) / 70ns (2.7V)
q
65,536 Words x16-bit Asynchtonous
q
Wide Temperature Range
s
DESCRIPTION
The SRM20W117LLTT/SLTT
2/7
is a 65,536 words x 16-bit asynchronous, random access memory on a monolithic
CMOS chip. Its very low standby power requirement makes it ideat for applications requiring non-volatile syorage
with back-up batteries. The asynchronous and static nature of the memory requires no external clock or refreshing
circuit. It is possible to contorol the date width by the data byte control. Both the Input and output ports are TTL
compatible and 3-state output allows easy expansion of memory capacity. The temperature range of the
SRM20W117LLTT/SLTT
2/7
is from –40 to 85°C, and it is suitable for the industrial products.
s
FEATURES
q
Fast Access time ........................ 120ns (at 1.8V) / 70ns (at 2.7V)
q
Low supply current ..................... LL Version, SL Version
q
Completely static ........................ No clock required
q
Supply voltage ............................ 1.8V to 3.6V
q
TTL compatible inputs and outputs
q
3-state output with wired-OR capability
q
Non-volatile storage with back-up batteries
q
Package ..................................... SRM20W117LLTT/SLTT
TSOP (II)-44pin (Plastic)
SRM20W117LLRT/SLRT
TSOP (II)-44pin-R1 (Plastic)
s
PIN CONFIGURATION
(TSOP (II) )
A4
A3
A2
A1
A0
CS
I/O1
I/O2
I/O3
I/O4
V
DD
V
SS
I/O5
I/O6
I/O7
I/O8
WE
A15
A14
A13
A12
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
V
SS
V
DD
I/O12
I/O11
I/O10
I/O9
N.C.
A8
A9
A10
A11
N.C.
SRM20W117LLTT/SLTT
s
BLOCK DIAGRAM
(TSOP (II)-R1)
A5
A6
A7
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
V
SS
V
DD
I/O12
I/O11
IO10
I/O9
N.C.
A8
A9
A10
A11
N.C.
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A4
A3
A2
A1
A0
CS
I/O1
I/O2
I/O3
I/O4
V
DD
V
SS
I/O5
I/O6
I/O7
I/O8
WE
A15
A14
A13
A12
N.C.
7
Y Decoder
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
SRM20W117LLRT/SLRT
Address Buffer
9
X Decoder
512
Memory Cell Array
512 x 128 x 16
128x16
128
Column Gate
CS
LB
UB
CS,LB,UB
Control
Logic
16
s
PIN DESCRIPTION
A0 to A15
WE
OE
CS
LB
UB
I/O1 to 16
V
DD
V
SS
NC
Address Input
Write Enable
Output Enable
Chip Select
LOWER Byte Enable
UPPER Byte Enable
Data I/O
Power Supply (1.8V to 3.6V)
Power Supply (0V)
No connection
OE
WE
OE, WE
Control
Logic
I/O Buffer
I/O1
I/O16
SRM20W117LLTT/SLTT
2/7
s
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply voltage
Input voltage
Input/Output voltage
Power dissipation
Operating temperature
Storage temperature
Soldering temperature and time
*
V
I
,V
I/O
Symbol
V
DD
V
I
V
I/O
P
D
T
opr
T
stg
T
sol
Ratings
– 0.5
*
to 4.6
– 0.5
*
to V
DD
+ 0.3
– 0.5
*
to V
DD
+ 0.3
0.5
– 40 to 85
– 65 to 150
260°C, 10s (at lead)
(V
SS
=0V)
Unit
V
V
V
W
°C
—
(Min.) = –3.0V (Pulse width is 50ns)
s
DC RECOMMENDED OPERATING CONDITIONS
Parameter
Supply voltage
Input voltege
*
if
Symbol
V
DD
V
SS
V
IH
V
IL
V
DD
= 1.8 to 3.0V
Max.
Min.
Typ.
3.0
1.8
2.0
0.0
0.0
0.0
V
DD
+0.3
0.8V
DD
–
–
0.3
– 0.3
*
(Ta = –40 to 85
°C)
V
DD
= 2.7 to 3.6V
Unit
Max.
Min.
Typ.
3.6
2.7
3.0
V
0.0
0.0
0.0
V
V
DD
+0.3
2.2
–
V
*
– 0.3
–
0.4
V
pulse width is less than 50ns it is – 3.0V
s
ELECTRICAL CHARACTERISTICS
q
DC Electrical Characteristics
Parameter
Input leakage current
Output leakage current
High level output voltage
Low level output voltage
Symbol
I
LI
I
LO
V
OH
V
OL
I
DDS
Standby supply current
I
DDS1
Conditions
V
I
= 0 to V
DD
LB and UB = V
IH
or
CS = V
IH
or WE = V
IL
or OE = V
IH
, V
I/O
= 0 to V
DD
I
OH
I
OL
2.0mA,V
DD
3.0V
100µA
2.0mA,V
DD
3.0V
100µA
(V
SS
=0V, Ta = –40 to 85
°C)
V
DD
= 2.7 to 3.6V
V
DD
= 1.8 to 3.0V
*1
Max. Min. Typ.
*2
Max. Unit
Min. Typ.
–
1.0 –1.0
–
1.0
µA
–1.0
–1.0
–
V
DD
–0.2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0.4
–
–
–
0.2
20
2.5
2.5
1.0
–1.0
–
–
–
–
–
–
–
–
–
0.6
–
–
–
0.3
35
3
3
1.0
–
–
0.4
0.2
2.0
60
20
4
2
30
10
2
1
45
5
5
µA
V
V
mA
2.4
–
– V
DD
–0.2
–
–
0.2
–
1.7
50
18
3.4
1.8
25
9
1.7
0.9
35
4
4
–
–
–
–
–
–
–
–
–
–
–
–
I
DDA
Average operating current
I
DDA1
Operating Supply Current
I
DDO
LB and UB
=
V
IH
or
CS
=
V
IH
–40 to 85
°C
–40 to 70
°C
LL
–40 to 40
°C
CS
≥
V
DD
– 0.2V or
25
°C
LB and UB
≥
V
DD
– 0.2V,
–40 to 85
°C
CS
≤
0.2V
–40 to 70
°C
SL
–40 to 40
°C
25
°C
V
I
= V
IL
or V
IH
I
I/O
= 0mA, t
cyc
= Min.
V
I
= V
IL
or V
IH
I
I/O
= 0mA, t
cyc
= 1µs
V
I
= V
IL
or V
IH
I
I/O
= 0mA
µA
µA
mA
mA
mA
*1 : Typical values are measured at Ta = 25°C and V
DD
= 2.0V
*2 : Typical values are measured at Ta = 25°C and V
DD
= 3.0V
q
Terminal Capacitance
Parameter
Address Capacitance
Input Capacitance
I/O Capacitance
Symbol
C
ADD
C
I
C
I/O
Conditions
V
I
= 0V
V
I
= 0V
V
I/O
= 0V
Min.
–
–
–
Typ.
–
–
–
(Ta = 25°C, f = 1MHz)
Max.
8
8
10
Unit
pF
pF
pF
Note : This parameter is made by the inspection data of sample, not of all products
2
SRM20W117LLTT/SLTT
2/7
q
AC Electrical Characteristics
r
Read Cycle
SRM20W117LLTT
2
/SLTT
2
Parameter
Read cycle time
Address access time
CS access time
OE access time
LB, UB access time
CS output set time
CS output floating
LB, UB output set time
LB, UB output floating
OE output set time
OE output floating
Output hold time
Symbol
t
RC
t
ACC
t
ACS
t
OE
t
AB
t
CLZ
t
CHZ
t
BLZ
t
BHZ
t
OLZ
t
OHZ
t
OH
Conditions
1
1
1
1
1
2
2
2
2
2
2
1
1.8 to 3.0V
Min.
120
–
–
–
–
10
–
10
–
5
–
10
Max.
–
120
120
70
120
–
40
–
40
–
40
–
Min.
70
–
–
–
–
5
–
5
–
0
–
10
(V
SS
= 0V, Ta = –40 to 85°C)
SRM20W117LLTT
7
/SLTT
7
2.7 to 3.6V
Max.
–
70
70
40
70
–
30
–
30
–
30
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
r
Write Cycle
Parameter
Write cycle time
Chip select time (CS)
Address enable time
Address setup time
Write pulse width
LB, UB select time
Address hold time
Data setup time
Data hold time
WE output floating
WE output set time
*1 Test Conditions
1. Input pulse level : 0.4V to 2.4V (3V)
0.3V to 0.8V
DD
(2V)
2. t
r
= t
f
= 5ns
3. Input and output timing reference levels :1.5V (3V)
:1/2V
DD
(2V)
4. Output load : C
L
=100pF (Includes Jig Capacitance)
output voltage level)
2. t
r
= t
f
= 5ns
(V
SS
= 0V, Ta = –40 to 85°C)
SRM20W117LLTT
2
/SLTT
2
1.8 to 3.0V
Min.
120
100
100
0
90
100
0
60
0
–
5
Max.
–
–
–
–
–
–
–
–
–
40
–
1. Input pulse level :
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
BW
t
WR
t
DW
t
DH
t
WHZ
t
OW
Conditions
1
1
1
1
1
1
1
1
1
2
2
SRM20W117LLTT
7
/SLTT
7
2.7 to 3.6V
Min.
70
60
60
0
55
60
0
35
0
–
5
0.4V to 2.4V (3V)
0.3V to 0.8V
DD
(2V)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Max.
–
–
–
–
–
–
–
–
–
30
–
*2 Test Conditions
3. Input timing reference levels :1.5V (3V)
:1/2V
DD
(2V)
4. Output timing reference levels :
±200mV
(the level displaced from stable
5. Output load :C
L
= 5pF (Includes Jig Capacitance)
1TTL
I/O
C
L
1TTL
I/O
C
L
3
SRM20W117LLTT/SLTT
2/7
q
Timing Chart
r
Read Cycle
*1
t
RC
A0 to 15
t
ACC
CS
LB, UB
OE
I/O1 to 16
(Dout)
t
CLZ
t
AB
t
BLZ
t
OLZ
t
OE
t
CHZ
t
BHZ
t
OHZ
t
ACS
t
OH
A0 to 15
t
AS
CS
LB, UB
WE
I/O1 to 16
(Dout)
(Din)
t
WHZ
t
DW
t
DH
t
AW
t
CW
t
WR
r
Write Cycle 1 (CS Control)
*2, *3
t
WC
r
Write Cycle 2 (WE Control)
*3
t
WC
A0 to 15
t
CW
CS
t
BW
LB, UB
t
AS
WE
I/O1 to 16
(Dout)
(Din)
t
WHZ
t
DW
t
WP
t
WR
t
OW
t
DH
r
Write Cycle 3 (UB, LB Control)
*3
t
WC
A0 to 15
CS
t
AS
LB, UB
WE
I/O1 to 16
(Dout)
(Din)
t
WP
t
BW
t
WR
t
DW
t
DH
Note :
During read cycle time, WE is to be "High" level.
In write cycle time that is controlled by CS, output buffer is to be "Hi-Z" state if OE is "Low" level.
*
3 When output buffer is in output state, be careful that do not input the opposite signals to the output data.
*
2
*
1
q
DATA RETENTION CHARACTERISTIC WITH LOW VOLTAGE POWER SUPPLY
(for just 3.0V operation)
(V
SS
= 0V, Ta = –40 to 85°C)
Parameter
Symbol
Data retention supply voltage V
DDR
I
DDR
Data retention curren
Conditions
–40 to 85°C
–40 to 70°C
V
DDR
= 3.0V, CS
≥
V
DD
– 0.2V LL
–40 to 40°C
or LB and UB
≥
V
DD
– 0.2V
+25°C
–40 to 85°C
CS
≤
0.2V
SL –40 to 70°C
–40 to 40°C
+25°C
Min.
2.0
–
–
–
–
–
–
–
–
0
5
Typ.
–
–
–
–
0.4
–
–
–
0.2
–
–
Max.
–
50
18
3.4
1.8
25
9
1.7
0.9
–
–
Unit
V
µA
Data hold time
Operation recovery time
t
CDR
t
R
ns
ms
Data retention timing 1 (CS Control)
V
DD
2.7V
t
CDR
V
DDR
≥
2.0V
Data hold time
CS
≥V
DD
– 0.2V
CS
V
IL
2.2V
2.7V
t
R
Data retention timing 2 (LB, UB Control)
V
DD
2.7V
t
CDR
LB
V
DDR
≥
2.0V
Data hold time
2.7V
t
R
2.2V
V
IL
and
UB
V
IL
2.2V
LB and UB
≥
V
DD
– 0.2V
2.2V
V
IL
4
SRM20W117LLTT/SLTT
2/7
s
FUNCTIONS
q
Truth Table
CS
H
X
L
L
L
L
L
L
L
L
L
X : High or Low
LB
X
H
L
H
L
L
H
L
L
L
H
UB
X
H
H
L
L
H
L
L
L
H
L
OE
X
X
X
X
X
L
L
L
H
H
H
WE
X
X
L
L
L
H
H
H
H
H
H
I/O1 to 8
High-Z
High-Z
Data In
High-Z
Data In
DataOut
High-Z
Data Out
High-Z
High-Z
High-Z
I/O9 to 16
High-Z
High-Z
High-Z
Data In
Data In
High-Z
DataOut
Data Out
High-Z
High-Z
High-Z
MODE
Not Selected
Not Selected
Lower Byte Write
Upper Byte Write
All Byte Write
Lower Byte Read
Upper Byte Read
All Byte Read
Output disable
Output disable
Output disable
I
DD
I
DDS,
I
DDS1
I
DDS,
I
DDS1
I
DDA,
I
DDA1
I
DDA,
I
DDA1
I
DDA,
I
DDA1
I
DDA,
I
DDA1
I
DDA,
I
DDA1
I
DDA,
I
DDA1
I
DDA,
I
DDA1
I
DDA,
I
DDA1
I
DDA,
I
DDA1
q
Reading data
It is possible to control the data width by LB and UB pins.
(1) Reading data from lower byte
Data is able to be read when the address is set while holding CS ="Low", OE= "Low", LB ="Low" and WE =
"High".
(2) Reading data from upper byte
Data is able to be read when the address is set while holding CS = "Low", OE = "Low", UB = "Low" and WE
="High".
(3) Reading data from both bytes
Data is able to be read when the address is set while holding CS = "Low", OE ="Low", UB ="Low", LB =
"Low", and WE = "High"
Since I/O pins are in "Hi-Z" state when OE = "High", the data bus line can be used for any other objective, then
access time apparently is able to be cut down.
q
Writing data
(1) Writing data into lower byte
There are the following three ways of writing data into memory.
i) Hold WE = "Low", UB = "High" and LB = "Low", set address and give "Low" pulse to CS.
ii) Hold CS = "Low", UB = "High" and LB = "Low", set address and give "Low" pulse to WE.
iii) Set address and give "Low" pulse to CS, UB = "High" and "Low" pulse to WE, LB.
Anyway, data on I/O pins are latched up into the memory cell during CS ="Low", WE ="Low", and LB = "Low".
(2) Writing data into upper byre
There are the following three ways of writing data into the memory.
i) Hold WE = "Low", LB = "High" and UB = "Low", set address and give "Low" pulse to CS.
ii) Hold CS = "Low", LB = "High" and UB = "Low", set address and give "Low" pulse to WE.
iii) Set address and give "Low" pulse to CS, LB = "High" and "Low" pulse to WE, UB.
Anyway, data on I/O pins are latched up into the memory cell during CS = "Low", WE = "Low", and UB = "Low".
(3)Writing data into both bytes
There are the following three ways of writing data into the memory.
i) Hold WE = "Low", LB and UB = "Low", set address and give "Low" pulse to CS.
ii) Hold CS = "Low", LB and UB = "Low", set address and give "Low" pulse to WE.
iii) Set address give "Low" pulse to both pins of LB and UB, "Low" pulse to CS and "Low" pulse to WE.
5
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