v1.0
Military ProASIC3/EL Low-Power Flash FPGAs
with Flash*Freeze Technology
Features and Benefits
Military Temperature Tested and Qualified
• Each Device Tested from –55°C to 125°C
®
Advanced and Pro (Professional) I/Os
††
•
•
•
•
•
•
•
•
•
•
•
•
•
•
700 Mbps DDR, LVDS-Capable I/Os
1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
†
Bank-Selectable I/O Voltages—up to 8 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and
LVCMOS 2.5 V / 5.0 V Input
†
Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS
Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL
2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3
Class I and II (A3PE3000L only)
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold-Sparing I/Os
Programmable Output Slew Rate and Drive Strength
Programmable Input Delay (A3PE3000L only)
Schmitt Trigger Option on Single-Ended Inputs (A3PE3000L)
Weak Pull-Up/-Down
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages across the Military ProASIC®3EL
Family
Firm-Error Immune
• Not Susceptible to Neutron-Induced Configuration Loss
Low Power
• Dramatic Reduction in Dynamic and Static Power
• 1.2 V to 1.5 V Core and I/O Voltage Support for Low Power
†
• Low Power Consumption in Flash*Freeze Mode Allows for
Instantaneous Entry To / Exit From Low-Power Flash*Freeze
Mode
ƒ
• Supports Single-Voltage System Operation
• Low-Impedance Switches
High Capacity
• 600 k to 3 M System Gates
• Up to 504 kbits of True Dual-Port SRAM
• Up to 620 User I/Os
Reprogrammable Flash Technology
•
•
•
•
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
Live-at-Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design when Powered Off
Clock Conditioning Circuit (CCC) and PLL
• Six CCC Blocks, One with Integrated PLL (ProASIC3) and All
with Integrated PLL (ProASIC3EL)
• Configurable
Phase
Shift, Multiply/Divide,
Delay
Capabilities, and External Feedback
• Wide Input Frequency Range 1.5 MHz to 250 MHz (1.2 V
systems) and 350 MHz (1.5 V systems)
High Performance
• 350 MHz (1.5 V systems) and 250 MHz (1.2 V systems) System
Performance
• 3.3 V, 66 MHz, 66-Bit PCI (1.5 V systems) and 66 MHz, 32-Bit
PCI (1.2 V systems)
SRAMs and FIFOs
• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,
and ×18 organizations available)
• True Dual-Port SRAM (except ×18)
• 24 SRAM and FIFO Configurations with Synchronous
Operation:
– 250 MHz: For 1.2 V Systems
– 350 MHz: For 1.5 V Systems
®
• ARM Cortex™-M1 Soft Processor Available with or without
Debug
A3P1000
M1A3P1000
1M
24,576
144
32
1k
Yes
1
18
4
154
PQ208
FG144
A3PE3000L
M1A3PE3000L
3M
75,264
504
112
1k
Yes
6
18
8
620
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
• FlashLock
®
to Secure FPGA Contents
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
• High-Performance, Low-Skew Global Network
• Architecture Supports Ultra-High Utilization
Table I-1 •
Military ProASIC3/EL Low-Power Devices
ProASIC3/EL Devices
ARM Cortex-M1
System Gates
VersaTiles (D-flip-flops)
RAM kbits (1,024 bits)
4,608-Bit Blocks
FlashROM Bits
Secure (AES) ISP
2
Integrated PLL in CCCs
VersaNet Globals
I/O Banks
Maximum User I/Os
Package Pins
Devices
1
600 k
13,824
108
24
1k
Yes
6
18
8
270
A3PE600L
ARM Processor Support in ProASIC3/EL FPGAs
PQFP
FBGA
FG484
Notes:
1. Refer to the
Cortex-M1
product brief for more information.
2. AES is not available for ARM-enabled ProASIC3/EL devices.
FG484, FG896
† A3P1000 only supports 1.5 V core operation.
ƒ Flash*Freeze technology is not available for A3P1000.
†† Pro I/Os are not available on A3P1000.
August 2008
© 2009 Actel Corporation
I
Military ProASIC3/EL Low-Power Flash FPGAs
I/Os Per Package
1
ProASIC3/EL
Low-Power
Devices
ARM
Cortex-M1
Devices
A3PE600L
A3P1000
A3PE3000L
M1A3P1000
M1A3PE3000L
Package
PQ208
FG144
FG484
FG896
Notes:
Single-
Ended I/O
2
–
–
270
–
Differential
I/O Pairs
–
–
135
–
Single-
Ended I/O
2
154
97
–
–
Differential
I/O Pairs
35
25
–
–
Single-
Ended I/O
2
–
–
341
620
Differential
I/O Pairs
–
–
168
300
1. When considering migrating your design to a lower- or higher-density device, refer to the packaging section of the
datasheet to ensure you are complying with design and board migration requirements.
2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
3. "G" indicates RoHS-compliant packages. Refer to
"Military ProASIC3/EL Ordering Information" on page III
for the
location of the "G" in the part number.
4. For A3PE3000L devices, the usage of certain I/O standards is limited as follows:
– SSTL3(I) and (II): up to 40 I/Os per north or south bank
– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank
– SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank
5. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular I/O, the number of single-
ended user I/Os available is reduced by one.
II
v1.0
Military ProASIC3/EL Low-Power Flash FPGAs
Military ProASIC3/EL Ordering Information
A3P1000
_
1
FG
G
144
M
Application (Temperature Range)
M = Military (
–
55°C to 125°C
Junction
Temperature)
Package Lead
Count
Lead-Free Packaging
Blank =
Standard
Packaging
G=
RoHS-Compliant (Green) Packaging
Package Type
FG = Fine Pitch Ball
Grid
Array (1.0 mm pitch)
PQ = Plastic Quad Flat Pack (0.5 mm pitch)
Speed Grade
Blank =
Standard
1 = 15% Faster than
Standard
Part Number
Military ProASIC3/EL Devices
A3PE600L =
600,000 System Gates
A3P1000 = 1,000,000
System Gates
A3PE3000L = 3,000,000
System Gates
Military ProASIC3/EL Devices with ARM Cortex-M1
M1A3P1000 = 1,000,000
System Gates
M1A3PE3000L = 3,000,000
System Gates
v1.0
III
Military ProASIC3/EL Low-Power Flash FPGAs
Temperature Grade Offerings
Package
ARM Cortex-M1 Devices
PQ208
FG144
FG484
FG896
–
–
M
–
A3PE600L
A3P1000
M1A3P1000
M
M
–
–
A3PE3000L
M1A3PE3000L
–
–
M
M
Note:
M = Military temperature range: –55°C to 125°C junction temperature
Speed Grade and Temperature Grade Matrix
Temperature Grade
M
Std.
–1
✓
✓
Note:
M = Military temperature range: –55°C to 125°C junction temperature
Contact your local Actel representative for device availability:
http://www.actel.com/contact/default.aspx.
IV
v1.0
1 – Military ProASIC3/EL Device Family Overview
General Description
The military ProASIC3/EL family of Actel flash FPGAs dramatically reduces dynamic power
consumption by 40% and static power by 50%. These power savings are coupled with
performance, density, true single chip, 1.2 V to 1.5 V core and I/O operation, reprogrammability,
and advanced features.
Actel's proven Flash*Freeze technology enables military ProASIC3EL device users to shut off
dynamic power instantaneously and switch the device to static mode without the need to switch
off clocks or power supplies, and retaining internal states of the device. This greatly simplifies
power management. In addition, optimized software tools using power-driven layout provide
instant push-button power reduction.
Nonvolatile flash technology gives military ProASIC3/EL devices the advantage of being a secure,
low-power, single-chip solution that is live at power-up (LAPU). Military ProASIC3/EL devices offer
dramatic dynamic power savings, giving FPGA users flexibility to combine low power with high
performance.
These features enable designers to create high-density systems using existing ASIC or FPGA design
flows and tools.
Military ProASIC3/EL devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM
storage as well as clock conditioning circuitry (CCC) based on an integrated phase-locked loop
(PLL). Military ProASIC3/EL devices support devices from 600 k system gates to 3 million system
gates with up to 504 kbits of true dual-port SRAM and 620 user I/Os.
M1 military ProASIC3/EL devices support the high-performance, 32-bit Cortex-M1 processor
developed by ARM for implementation in FPGAs. ARM Cortex-M1 is a soft processor that is fully
implemented in the FPGA fabric. It has a three-stage pipeline that offers a good balance between
low-power consumption and speed when implemented in an M1 military ProASIC3/EL device. The
processor runs the ARMv6-M instruction set, has a configurable nested interrupt controller, and can
be implemented with or without the debug block. ARM Cortex-M1 is available at no cost from
Actel for use in M1 military ProASIC3/ELFPGAs.
The ARM-enabled devices have Actel ordering numbers that begin with M1 and do not support
AES decryption.
Flash*Freeze Technology
†
Military ProASIC3EL devices offer Actel's proven Flash*Freeze technology, which allows
instantaneous switching from an active state to a static state. When Flash*Freeze mode is
activated, military ProASIC3EL devices enter a static state while retaining the contents of registers
and SRAM. Power is conserved without the need for additional external components to turn off
I/Os or clocks. Flash*Freeze technology is combined with in-system programmability, which enables
users to quickly and easily upgrade and update their designs in the final stages of manufacturing
or in the field. The ability of military ProASIC3EL devices to support a 1.2 V core voltage allows for
an even greater reduction in power consumption, which enables low total system power.
When the military ProASIC3EL device enters Flash*Freeze mode, the device automatically shuts off
the clocks and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity
resumes and data is retained.
The availability of low-power modes, combined with a reprogrammable, single-chip, single-voltage
solution, make military ProASIC3EL devices suitable for low-power data transfer and manipulation
in military-temperature applications where available power may be limited (e.g., in battery-
powered equipment); or where heat dissipation may be limited (e.g., in enclosures with no forced
cooling).
†
Flash*Freeze technology is not supported on A3P1000.
v1.0
1-1
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