IDT74LVCH16721A
3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 20-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS,
5 VOLT TOLERANT I/O
AND BUS-HOLD
FEATURES:
Typical
t
SK(0)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– 0.635mm pitch SSOP, 0.50mm pitch TSSOP
and 0.40mm pitch TVSOP packages
– Extended commercial range of -40°C to +85°C
– V
CC
= 3.3V ±0.3V, Normal Range
– V
CC
= 2.7V to 3.6V, Extended Range
– CMOS power levels (0.4µ W typ. static)
– All inputs, outputs and I/O are 5 Volt tolerant
– Supports hot insertion
Drive Features for LVCH16721A:
– High Output Drivers:
±24mA
– Reduced system switching noise
–
–
IDT74LVCH16721A
DESCRIPTION:
This 20-bit flip-flop is built using advanced dual metal CMOS technology.
The 20 flip-flops of the LVCH16721A are edge-triggered D-type flip-flops
with qualified clock storage. On the positive transition of the clock (CLK)
input, the device provides true data at the Q outputs if the clock-enable
(CLKEN) input is low. If
CLKEN
is high, no data is stored.
A buffered output-enable (OE) input places the 20 outputs in either a
normal logic state (high or low) or a high-impedance state. In the high-
impedance state, the outputs neither load nor drive the bus lines significantly.
The high-impedance state and increased drive provide the capability to
drive bus lines without the need for interface or pullup components.
OE
does
not affect the internal operation of the flip-flops. Old data can be retained or
new data can be entered while the outputs are in the high-impedance state.
The LVCH16721A has been designed with a
±
24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The LVCH16721A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
OE
1
56
CLK
CLKEN
29
CE
C1
2
Q
1
55
D
1
1D
To 19 Other Channels
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
OCTOBER 1999
DSC-4936/-
IDT74LVCH16721A
3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
OE
Q
1
Q
2
GND
Q
3
Q
4
V
CC
Q
5
Q
6
Q
7
GND
Q
8
Q
9
Q
10
Q
11
Q
12
Q
13
GND
Q
14
Q
15
Q
16
V
CC
Q
17
Q
18
GND
Q
19
Q
20
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
SO56-1
14 SO56-2
SO56-3
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
CLK
D
1
D
2
GND
D
3
D
4
V
CC
D
5
D
6
D
7
GND
D
8
D
9
D
10
D
11
D
12
D
13
GND
D
14
D
15
D
16
V
CC
D
17
D
18
GND
D
19
D
20
CLKE N
ABSOLUTE MAXIMUM RATINGS
Symbol
V
TERM(2)
V
TERM(3)
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Description
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
O
< 0
Continuous Current through
each V
CC
or GND
(1)
Unit
V
V
°C
mA
mA
mA
LVC Link
Max.
– 0.5 to +6.5
– 0.5 to +6.5
– 65 to +150
– 50 to +50
– 50
±100
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
CAPACITANCE
(T
A
= +25
o
C, f = 1.0MHz)
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output
Capacitance
I/O Port
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
4.5
6.5
6.5
Max.
6
8
8
Unit
pF
pF
pF
LVC Link
NOTE:
1. As applicable to the device type.
FUNCTION TABLE
(each flip-flop)
(1)
Inputs
OE
L
L
L
L
H
CLKEN
H
L
L
L
X
CLK
X
↑
↑
L or H
X
Dx
X
H
L
X
X
Outputs
Qx
Q
0
H
L
Q
0
Z
SSOP/ TSSOP/ TVSOP
TOP VIEW
PIN DESCRIPTION
Pin Names
OE
Dx
Qx
CLK
CLKEN
NC
Description
3–State Output Enable Input (Active LOW)
Data Inputs
(1)
3-State Outputs
Clock Input
Clock Enable Input (Active LOW)
No Internal Connection
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
Q
0
= Level of Q before the indicated steady-state input conditions
were established.
NOTE:
1. These pins have “Bus-hold”. All other pins are standard inputs,
outputs, or I/Os.
c 1998 Integrated Device Technology, Inc.
2
DSC-123456
IDT74LVCH16721A
3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= –40
O
C to +85
O
C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
I
OFF
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input Leakage Current
High Impedance Output Current
(3-State Output pins)
Input/Output Power Off Leakage
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 0V, V
IN
or V
O
≤
5.5V
V
CC
= 2.3V, I
IN
= – 18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
3.6
≤
V
IN
≤
5.5V
(2)
Quiescent Power Supply
Current Variation
One input at V
CC
- 0.6V
other inputs at V
CC
or GND
—
—
—
—
—
—
—
– 0.7
100
—
—
—
±50
– 1.2
—
10
10
500
µA
LVC Link
Test Conditions
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= 0 to 5.5V
V
O
= 0 to 5.5V
Min.
1.7
2
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
Max.
—
—
0.7
0.8
±5
±10
Unit
V
V
µA
µA
µA
V
mV
µA
NOTES:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
2. This applies in the disabled state only.
BUS-HOLD CHARACTERISTICS
Symbol
I
BHH
I
BHL
I
BHH
I
BHL
I
BHHO
I
BHLO
LVC Link
Parameter
(1)
Bus-Hold Input Sustain Current
Bus-Hold Input Sustain Current
Bus-Hold Input Overdrive Current
V
CC
= 3.0V
V
CC
= 2.3V
V
CC
= 3.6V
Test Conditions
V
I
= 2.0V
V
I
= 0.8V
V
I
= 1.7V
V
I
= 0.7V
V
I
= 0 to 3.6V
Min.
– 75
75
—
—
—
Typ.
(2)
—
—
—
—
—
Max.
—
—
—
—
± 500
Unit
µA
µA
µA
NOTES:
1. Pins with Bus-hold are identified in the pin description.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
3
IDT74LVCH16721A
3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
Test Conditions
(1)
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 6mA
I
OH
= – 12mA
Min.
V
CC
– 0.2
2
1.7
2.2
2.4
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
V
CC
= 2.7V
V
CC
= 3.0V
I
OL
= 12mA
I
OL
= 24mA
2.2
—
—
—
—
—
Max.
—
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
LVC Link
Unit
V
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
V
CC
= 3.0V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate V
CC
range. T
A
= – 40°C to +85°C.
OPERATING CHARACTERISTICS, TA = 25°C
V
CC
= 2.5V ±0.2V
Symbol
Parameter
C
PD
Power Dissipation Capacitance Outputs enabled
C
PD
Power Dissipation Capacitance Outputs disabled
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
—
—
V
CC
= 3.3V±0.3V
Typical
—
—
Unit
pF
pF
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.5V±0.2V
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
SU
t
H
t
H
t
W
t
SK
(o)
Parameter
Propagation Delay
CLK to Qx
Output Enable Time
OE
to Qx
Output Disable Time
OE
to Qx
Set-up Time, data before CLK↑
Set-up Time,
CLKEN
before CLK↑
Hold Time, data after CLK
Hold Time,
CLKEN
after CLK
Pulse Duration, CLK HIGH or LOW
Output Skew
(2)
Min.
—
—
—
—
—
—
—
—
—
Max.
—
—
—
—
—
—
—
—
—
V
CC
= 2.7V
Min.
2
1.5
1.5
3.6
3.1
0
0
3.3
—
Max.
6
7
5.3
—
—
—
—
—
—
V
CC
= 3.3V±0.3V
Min.
2
1.5
1.5
3.1
2.7
0
0
3.3
—
Max.
5.2
6
5
—
—
—
—
—
500
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ps
NOTES:
1. See test circuits and waveforms. T
A
= – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74LVCH16721A
3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
PROPAGATION DELAY
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC
(1)
= 3.3V ±0.3V
6
2.7
1.5
300
300
50
V
CC
(1)
= 2.7V
6
2.7
1.5
300
300
50
V
CC
(2)
= 2.5V ±0.2V Unit
2 x Vcc
V
Vcc
V
CC
/ 2
150
150
30
V
V
mV
mV
pF
LVC Link
SAME PHAS E
IN P U T T R A N S IT IO N
t
P LH
O U T PU T
t
P LH
O P P O S IT E P H A S E
IN P U T T R A N S IT IO N
t
P H L
t
P H L
V
IH
V
T
0V
V
OH
V
T
V
OL
V
IH
V
T
0V
LVC Lin k
TEST CIRCUITS FOR ALL OUTPUTS
V
CC
500
Ω
P ulse
(1, 2)
G e n erato r
V
IN
D .U .T .
500
Ω
C
L
V
OUT
V
LO A D
O pen
GND
ENABLE AND DISABLE TIMES
EN ABLE
C O N TR O L
IN P U T
t
P ZL
O U T PU T
SW IT C H
N O R M A LLY
C LO SE D
LOW
t
P Z H
O U T PU T
SW IT C H
N O R M A LLY
OPEN
H IG H
V
LO A D /2
V
T
t
P H Z
V
T
0V
t
P LZ
D IS A B L E
V
IH
V
T
0V
V
LO A D /2
V
LZ
V
OL
V
OH
V
HZ
0V
LVC L ink
R
T
DEFINITIONS:
LV C Link
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
2. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2ns; t
R
≤
2ns.
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
SET-UP, HOLD, AND RELEASE TIMES
D A TA
IN P U T
T IM IN G
IN P U T
A S Y N C H RO N O U S
C O N TR O L
S Y N C H RO N O U S
C O N TR O L
t
R E M
t
S U
t
H
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
LV C Link
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
Switch
V
LOAD
GND
Open
LVC Link
t
S U
OUTPUT SKEW - tsk (x)
V
IH
IN P U T
V
T
0V
V
OH
V
T
OUTPUT 1
t
S K
(x)
t
S K
(x)
V
OL
V
OH
OUTPUT 2
t
P LH 2
t
P H L2
V
T
V
OL
t
H
PULSE WIDTH
LO W -H IG H -LO W
P U LS E
t
W
H IG H -L O W -H IG H
P U LS E
V
T
LV C Link
t
P LH 1
t
P H L1
V
T
t
S K
(x)
= t
P LH 2
-
t
P LH 1
o r
t
P H L2
-
t
P H L1
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
LV C Link
5
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