IDT74ALVC32
3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-OR GATE
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS
QUADRUPLE 2-INPUT
POSITIVE-OR GATE
FEATURES:
–
–
–
–
–
–
–
–
0.5 MICRON CMOS Technology
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
V
CC
= 3.3V ± 0.3V, Normal Range
V
CC
= 2.7V to 3.6V, Extended Range
V
CC
= 2.5V ± 0.2V
CMOS power levels (0.4µ W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in SOIC, SSOP and TSSOP packages
IDT74ALVC32
DESCRIPTION:
This quadruple 2-input positive-OR gate is built using advanced dual
metal CMOS technology. The ALVC32 performs the Boolean function
Y = A • B or Y = A + B in positive logic.
The ALVC32 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
Drive Features for ALVC32:
– High Output Drivers: ±24mA
– Suitable for heavy loads
APPLICATIONS:
•
3.3V High Speed Systems
•
3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
1
A
1
2
3
4
5
6
7
14
13
12
SO14-1
SO14-2 11
SO14-3
10
9
8
V
CC
4
B
4
A
4
Y
3
B
3
A
3
Y
A
Y
B
1
B
1
Y
2
A
2
B
2
Y
GN D
SOIC/ SSOP/ TSSOP
TOP VIEW
PIN DESCRIPTION
Pin Names
xA, xB
xY
Description
Data Inputs
Data Outputs
FUNCTION TABLE
Inputs
xA
H
X
L
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
(each gate)
(1)
Output
xY
H
H
L
xB
X
H
L
INDUSTRIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
SEPTEMBER 2000
DSC-4638/-
IDT74ALVC32
3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-OR GATE
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM(2)
V
TERM(3)
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Description
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
I
>
V
CC
Continuous Clamp Current, V
O
< 0
Continuous Current through each
V
CC
or GND
ALVC QUAD Link
CAPACITANCE
Unit
V
V
°C
mA
mA
mA
mA
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output Capacitance
(TA = +25°C, f = 1.0MHz)
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
5
7
7
Max.
7
9
9
Unit
pF
pF
pF
ALVC QUAD Link
Max.
– 0.5 to + 4.6
– 0.5 to V
CC
+ 0.5
– 65 to + 150
– 50 to + 50
± 50
– 50
±100
I/O Port Capacitance
NOTE:
1. As applicable to the device type.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
=
−40°C
to +85°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
IK
V
H
I
CCL
I
CCH
∆I
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input HIGH Current
Input LOW Current
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
Quiescent Power Supply
Current Variation
Test Conditions
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
CC
= 2.3V, I
IN
= – 18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
One input at V
CC
−
0.6V,
other inputs at V
CC
or GND
V
I
= V
CC
V
I
= GND
Min.
1.7
2
—
—
—
—
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
– 0.7
100
0.1
—
Max.
—
—
0.7
0.8
±5
±5
– 1.2
—
10
750
V
mV
µA
µA
ALVC QUAD Link
Unit
V
V
µA
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
c
2
IDT74ALVC32
3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-OR GATE
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
Test Conditions
(1)
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 6mA
I
OH
= – 12mA
Min.
V
CC
– 0.2
2
1.7
2.2
2.4
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
V
CC
= 2.7V
V
CC
= 3.0V
I
OL
= 12mA
I
OL
= 24mA
2
—
—
—
—
—
Max.
—
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
ALVC QUAD Link
Unit
V
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
V
CC
= 3.0V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate V
CC
range. T
A
= – 40°C to + 85°C.
OPERATING CHARACTERISTICS, T
A
= 25
o
C
V
CC
= 2.5V ± 0.2V
Symbol
C
PD
Parameter
Power Dissipation Capacitance per gate
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
24
V
CC
= 3.3V ± 0.3V
Typical
26
Unit
pF
SWITCHING CHARACTERISTICS
Symbol
t
PLH
t
PHL
Parameter
Propagation Delay
xA or xB to xY
(1)
V
CC
= 2.5V ± 0.2V
Min.
1
Max.
3.1
V
CC
= 2.7V
Min.
1
Max.
3.4
V
CC
= 3.3V ± 0.3V
Min.
1
Max.
3.3
Unit
ns
NOTE:
1. See test circuits and waveforms. T
A
= – 40°C to + 85°C.
3
IDT74ALVC32
3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-OR GATE
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
PROPAGATION DELAY
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC
(1)
= 3.3V ± 0.3V
6
2.7
1.5
300
300
50
V
CC
(1)
= 2.7V
6
2.7
1.5
300
300
50
V
CC
(2)
= 2.5V ± 0.2V Unit
2 x Vcc
V
Vcc
Vcc / 2
150
150
30
V
V
mV
mV
pF
ALVC QUAD Link
SAME PHASE
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PHL
t
PHL
V
IH
V
T
0V
V
OH
V
T
V
OL
V
IH
V
T
0V
ALVC Link
TEST CIRCUITS FOR ALL OUTPUTS
V
CC
500
Ω
Pulse
Generator
(1, 2)
ENABLE AND DISABLE TIMES
ENABLE
CONTROL
INPUT
t
PZL
OUTPUT
SW ITCH
NORMALLY
CLOSED
LOW
t
PZH
OUTPUT
SW ITCH
NORMALLY
OPEN
HIGH
V
LOAD/2
V
T
t
PHZ
V
T
0V
t
PLZ
DISABLE
V
IH
V
T
0V
V
LOAD/2
V
OL
+ V
LZ
V
OL
V
OH
V
OH -
V
HZ
0V
V
LOAD
Open
GND
V
IN
D.U.T.
V
OUT
R
T
500
Ω
C
L
ALVC Link
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
2. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2ns; t
R
≤
2ns.
ALVC Link
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
SET-UP, HOLD, AND RELEASE TIMES
DATA
INPUT
t
SU
t
H
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
ALVC Link
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
Switch
V
LOAD
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
ALVC QUAD Link
t
REM
GND
Open
t
SU
t
H
OUTPUT SKEW -
TSK
(x)
INPUT
t
PLH1
t
PHL1
V
IH
V
T
0V
V
OH
PULSE WIDTH
LOW-HIGH-LOW
PULSE
t
W
HIGH-LOW -HIGH
PULSE
V
T
ALVC Link
OUTPUT 1
t
SK
(x)
t
SK
(x)
V
T
V
OL
V
OH
V
T
OUTPUT 2
t
PLH2
t
PHL2
V
T
V
OL
t
SK
(x)
= t
PLH2
-
t
P LH1
or
t
PHL2
-
t
PHL1
NOTES:
ALVC Link
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
4
IDT74ALVC32
3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-OR GATE
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
XX
Tem p. R ange
ALVC
XXX
Device Type
XX
Package
DC
PY
PG
32
Sm all Outline IC (SO 14-1)
Shrink Sm all Outline Package (SO14-2)
Thin Shrink Sm all Outline Package (SO14-3)
Quadruple 2-Input Positive-OR Gate, ±24mA
74
– 40°C to +85°C
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www.idt.com*
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The IDT logo is a registered trademark of Integrated Device Technology, Inc.
5
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