White Electronic Designs
WV3HG32M72EER-AD6
PRELIMINARY*
256MB – 32Mx72 DDR2 SDRAM REGISTERED, w/PLL
FEATURES
240-pin, dual in-line memory module
Fast data transfer rates: PC2-4300 and PC2-3200
Utilizes 533 and 400 MT/s DDR2 SDRAM
components
V
CC
= V
CCQ
= 1.8V
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
DLL to align DQ and DQS transitions with CK
Multiple internal device banks for concurrent
operation
Supports duplicate output strobe (RDQS/RDQS#)
Programmable CAS# latency (CL): 3 and 4
Adjustable data-output drive strength
On-die termination (ODT)
Posted CAS# latency: 0, 1, 2, 3 and 4
Serial Presence Detect (SPD) with EEPROM
64ms: 8,192 cycle refresh
Gold edge contacts
RoHS compliant
Package option
• 240 Pin DIMM
• PCB – 18.29mm (0.720") Max
* This product is under development, is not qualified or characterized and is subject to
change without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
DESCRIPTION
The WV3HG32M72EER is a 32Mx72 Double Data
Rate DDR2 SDRAM high density module. This memory
module consists of nine 32Mx8 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
240-pin DIMM FR4 substrate.
OPERATING FREQUENCIES
PC2-3200
Clock Speed
CL-t
RCD
-t
RP
200MHz
3-3-3
PC2-4300
266MHz
4-4-4
September 2005
Rev. 1
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
PIN CONFIGURATION
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Symbol
V
REF
V
SS
DQ0
DQ1
V
SS
DQS0#
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
V
SS
RESET#
NC
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2#
DQS2
V
SS
DQ18
DQ19
V
SS
DQ24
DQ25
V
SS
DQS3#
DQS3
V
SS
DQ26
DQ27
V
SS
CB0
CB1
V
SS
DQS8#
DQS8
V
SS
CB2
CB3
V
SS
V
CCQ
CKE0
V
CC
NC
NC
V
CCQ
A11
A7
V
CC
A5
Pin No.
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Symbol
A4
V
CCQ
A2
V
CC
V
SS
V
SS
V
CC
NC
V
CC
A10/AP
BA0
V
CCQ
WE#
CAS#
V
CCQ
NC
NC
V
CCQ
V
SS
DQ32
DQ33
V
SS
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
V
SS
DQS5#
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
SA2
NC
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7#
DQS7
V
SS
DQ58
DQ59
V
SS
SDA
SCL
Pin No.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Symbol
V
SS
DQ4
DQ5
V
SS
DM0/DQS9
DM0/DQS9#
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1/DQS10
NC/DQS10#
V
SS
NC
NC
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2/DQS11
NC/DQS11#
V
SS
DQ22
DQ23
V
SS
DQ28
DQ29
V
SS
DM3/DQS12
NC/DQS12#
V
SS
DQ30
DQ31
V
SS
CB4
CB5
V
SS
DM8/DQS17
NC/DQS17#
V
SS
CB6
CB7
V
SS
V
CCQ
NC
V
CC
NC
NC
V
CCQ
A12
A9
V
CC
A8
A6
Pin No.
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Symbol
V
CCQ
A3
A1
V
CC
CK0
CK0#
V
CC
A0
V
CC
BA1
V
CCQ
RAS#
S0#
V
CCQ
ODT0
NC
V
CC
V
SS
DQ36
DQ37
V
SS
DM4/DQS13
NC/DQS13#
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
DM5/DQS14
NC/DQS14#
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
NC
NC
V
SS
DM6/DQS15
NC/DQS15#
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DM7/DQS16
NC/DQS16#
V
SS
DQ62
DQ63
V
SS
V
CC
SPD
SA0
SA1
2
WV3HG32M72EER-AD6
PRELIMINARY
PIN NAMES
Pin Name
A0-A12
BA0,BA1
DQ0-DQ63
CB0-CB7
DQS0-DQS17
DQS0#-DQS17#
ODT0
CK0,CK0#
CKE0
S0#
RAS#
CAS#
WE#
RESET#
V
CC
V
CCQ
V
SS
SA0-SA2
SDA
SCL
DM0-DM8
V
REF
V
CC
SPD
NC
Function
Address Inputs
SDRAM Bank Address
Data Input/Output
Check Bits
Data strobes
Data strobes complement
On-die termination control
Clock Inputs, positive line
Clock Enables
Chip Selects
Row Address Strobe
Column Address Strobe
Write Enable
Register Reset Input
Core and I/O Power (1.8V)
I/O Power (1.8V)
Ground
SPD address
SPD Data Input/Output
Serial Presence Detect(SPD) Clock Input
Data Masks
Input/Output Reference
SPD Power
Spare pins, No connect
September 2005
Rev. 1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG32M72EER-AD6
PRELIMINARY
FUNCTIONAL BLOCK DIAGRAM
RS0
DQS0
DQS0#
DM0/DQS9
NC/DQS9#
DM/
NU/ CS# DQS DQS#
RDQS RDQS#
DQS4
DQS4#
DM4/DQS13
NC/DQS13#
DM/
NU/ CS# DQS DQS#
RDQS RDQS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DQS1#
DM1/DQS10
NC/DQS10#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS5
DQS5#
DM5/DQS14
NC/DQS14#
DM/
NU/ CS# DQS DQS#
RDQS RDQS#
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM/
NU/ CS# DQS DQS#
RDQS RDQS#
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS2#
DM2/DQS11
NC/DQS11#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS6
DQS6#
DM6/DQS15
NC/DQS15#
DM/
NU/ CS# DQS DQS#
RDQS RDQS#
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM/
NU/ CS# DQS DQS#
RDQS RDQS#
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DQS3#
DM3/DQS12
NC/DQS12#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS7
DQS7#
DM7/DQS16
NC/DQS16#
DM/
NU/ CS# DQS DQS#
RDQS RDQS#
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM/
NU/ CS# DQS DQS#
RDQS RDQS#
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS8
DQS8#
DM8/DQS17
NC/DQS17#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
Serial PD
SCL
NU/ CS# DQS DQS#
DM/
RDQS RDQS#
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
V
CCSPD
Serial PD
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
SDA
WP A0
A1
A2
V
CC
/V
CCQ
V
REF
V
SS
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
SA0 SA1 SA2
CK0
CK0#
RESET#
P
L
L
OE
PCK0-PCK6, PCK8, PCK9 - > CK : DDR2 SDRAMs
PCK0#-PCK6#, PCK8#, PCK9# - > CK# : DDR2 SDRAMs
PCK7 -> CK : Register
PCK7# -> CK# : Register
CS0#
BA0-BA1
A0-A12
RAS#
CAS#
WE#
CKE0
ODT0
RESET*#
PCK7*
PCK7*#
1:2
R
E
G
I
S
T
E
R
RST#
RCS0# : DDR2 SDRAMs
RBA0-RBA1 : DDR2 SDRAMs
RA0-RA12 : DDR2 SDRAMs
RRAS# : DDR2 SDRAMs
RCAS# : DDR2 SDRAMs
RWE# : DDR2 SDRAMs
RCKE0 : DDR2 SDRAMs
RODT0 : DDR2 SDRAMs
Notes :
1. DQ-to-I/O wiring may be changed per nibble.
2. Unless otherwise noted, resister values are 22 Ohms
3. RS0# and RS1# alternate between the back and
front sides of the DIMM
* RESET#, PCK7 and PCK7# connects to both registers. Other signals connect to one of two registers.
September 2005
Rev. 1
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
DC OPERATING CONDITIONS
All voltages referenced to V
SS
Parameter
Supply voltage
I/O Supply voltage
V
CCL
Supply voltage
I/O Reference voltage
I/O Termination voltage
Symbol
V
CC
V
CCQ
V
CCL
V
REF
V
TT
Min
1 .7
1 .7
1 .7
0.49 x V
CCQ
V
REF
-0.04
Typical
1 .8
1 .8
1 .8
0.50 x V
CCQ
V
REF
WV3HG32M72EER-AD6
PRELIMINARY
Max
1 .9
1 .9
1 .9
0.51 x V
CCQ
V
REF
+ 0.04
Unit
V
V
V
V
V
Notes
1
4
4
2
3
Notes:
1. V
CC
V
CCQ
must track each other. V
CCQ
must be less than or equal to V
CC
.
2. V
REF
is expected to equal V
CCQ
/2 of the transmitting device and to track variations in the DC level of the same. Peak-topeak noise on V
REF
may not excedd ±1 percent of the DC
value. Peak-to-peak AC noise on V
REF
may not exceed ±2 percent of V
REF
. This measurement is to be taken at the nearest V
REF
bypass capacitor.
3. V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to be set equal to V
REF
and must track variations in the DC level of V
REF
.
4. V
CCQ
tracks with V
CC
; V
CCL
track with V
CC
.
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
CCQ
V
CCL
V
IN
, V
OUT
T
STG
T
CASE
Parameter
Voltage on V
CC
pin relative to V
SS
Voltage on V
CCQ
pin relative to V
SS
Voltage on V
CCL
pin relative to V
SS
Voltage on any pin relative to V
SS
Storage temperature
Device operating Temperatue temperature
Command/Address,
RAS#, CAS#, WE#,
CS#, CKE
CK, CK#
DM
DQ, DQS, DQS#
MIN
-1.0
-0.5
-0.5
-0.5
-55
0
-5
-10
-5
-5
-18
MAX
2.3
2.3
2.3
2.3
100
85
5
10
5
5
18
U nit
V
V
V
V
°C
°C
uA
uA
uA
uA
uA
I
L
Input leakage current; Any input 0V<V
IN
<V
CC
; V
REF
input
0V<V
IN
<0.95V; Other pins not under test = 0V
I
OZ
I
VREF
Output leakage current;
0V<V
OUT
<V
CCQ
; DQs and ODT are disable
V
REF
leakage current; V
REF
= Valid V
REF
level
INPUT/OUTPUT CAPACITANCE
T
A
= 25°C, f = 1MHz, V
CC
= V
CCQ
= 1.8V
Parameter
Input capacitance (A0 - A12, BA0 - BA1 ,RAS#,CAS#,WE#)
Input capacitance ( CKE0), (ODT0)
Input capacitance (CS0#)
Input capacitance (CK0, CK0#)
Input capacitance (DM0 - DM8), (DQS0 - DQS17)
Input capacitance (DQ0 - DQ63), (CB0 - CB7)
Symbol
C
IN1
C
IN2
C
IN3
C
IN4
C
IN5
C
OUT1
Min
6.5
6.5
6.5
6
6.5
6.5
Max
7.5
7.5
7.5
7
8
8
Unit
pF
pF
pF
pF
pF
pF
September 2005
Rev. 1
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG32M72EER-AD6
PRELIMINARY
OPERATING TEMPERATURE CONDITION
Parameter
Operating temperature
Symbol
T
OPER
Rating
0 to 85
Units
°C
Notes
1, 2
Notes:
1. Operating temperature is the case surface temperature on the center/top side ofthe DRAM. Forthe measurement conditions, please refer to JEDEC JESD51 .2
2. At 0 - 85°C, operation temperature range, all DRAM specification will be supported.
INPUT DC LOGIC LEVEL
All voltages referenced to V
SS
Parameter
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Symbol
V
IH
(DC)
V
IL
(DC)
Min
V
REF
+ 0.1 25
-0.300
Max
V
REF
+ 0.300
V
REF
- 0.125
Unit
V
V
INPUT AC LOGIC LEVEL
All voltages referenced to V
SS
Parameter
AC Input High (Logic 1) Voltage
AC Input Low (Logic 0) Voltage DDR2-400 & DDR2-533
Symbol
V
IH
(AC)
V
IL
(AC)
Min
V
REF
+ 0.250
—
Max
—
V
REF
- 0.250
Unit
V
V
September 2005
Rev. 1
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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