SST26VF064B / SST26VF064BA
3.0V Serial Quad I/O (SQI) Flash Memory
Features
• Single Voltage Read and Write Operations
- 2.7-3.6V
• Serial Interface Architecture
- Nibble-wide multiplexed I/O’s with SPI-like serial
command structure
- Mode 0 and Mode 3
- x1/x2/x4 Serial Peripheral Interface (SPI) Proto-
col
• High Speed Clock Frequency
- 104 MHz max
• Burst Modes
- Continuous linear burst
- 8/16/32/64 Byte linear burst with wrap-around
• Superior Reliability
- Endurance: 100,000 Cycles (min)
- Greater than 100 years Data Retention
• Low Power Consumption:
- Active Read current: 15 mA (typical @ 104 MHz)
- Standby Current: 15 µA (typical)
• Page-Program
- 256 Bytes per page in x1 or x4 mode
• End-of-Write Detection
- Software polling the BUSY bit in status register
• Flexible Erase Capability
- Uniform 4 KByte sectors
- Four 8 KByte top and bottom parameter overlay
blocks
- One 32 KByte top and bottom overlay block
- Uniform 64 KByte overlay blocks
• Write-Suspend
- Suspend Program or Erase operation to access
another block/sector
• Software Reset (RST) mode
• Software Write Protection
- Individual Block-Locking
- 64 KByte blocks, two 32 KByte blocks, and
eight 8 KByte parameter blocks
• Security ID
- One-Time Programmable (OTP) 2 KByte,
Secure ID
- 64 bit unique, factory pre-programmed
identifier
- User-programmable area
• Temperature Range
- Industrial: -40°C to +85°C
• Packages Available
- 8-contact WSON (6mm x 5mm)
- 8-lead SOIC (200 mil)
- 16-lead SOIC (300 mil)
- 24-ball TBGA (6mm x 8mm)
• All devices are RoHS compliant
Product Description
The Serial Quad I/O™ (SQI™) family of flash-memory
devices features a six-wire, 4-bit I/O interface that
allows for low-power, high-performance operation in a
low pin-count package. SST26VF064B/064BA also
support full command-set compatibility to traditional
Serial Peripheral Interface (SPI) protocol. System
designs using SQI flash devices occupy less board
space and ultimately lower system costs.
All members of the 26 Series, SQI family are manufac-
tured with proprietary, high-performance CMOS Super-
Flash® technology. The split-gate cell design and thick-
oxide tunneling injector attain better reliability and man-
ufacturability compared with alternate approaches.
The SST26VF064B/064BA significantly improve per-
formance and reliability, while lowering power con-
sumption. These devices write (Program or Erase) with
a single power supply of 2.7-3.6V. The total energy
consumed is a function of the applied voltage, current,
and time of application. Since for any given voltage
range, the SuperFlash technology uses less current to
program and has a shorter erase time, the total energy
consumed during any Erase or Program operation is
less than alternative flash memory technologies.
SST26VF064B/064BA are offered in 8-contact WSON
(6 mm x 5 mm), 8-lead SOIC (200 mil), 16-lead SOIC
(300 mil), and 24-ball TBGA. See
Figure 2-2
for pin
assignments.
Two configurations are available upon order:
SST26VF064B default at power-up has the WP# and
Hold# pins enabled and SST26VF064BA default at
power-up has the WP# and Hold# pins disabled.
2013 Microchip Technology Inc.
Advance Information
DS25119C-page 1
SST26VF064B / SST26VF064BA
Top View
4
NC
3
NC
2
NC
1
NC
NC
NC
NC
NC
NC
SCK
CE#
S0/
SIO1
NC
NC
V
SS
NC
SI/
SIO0
NC
NC
V
DD
WP#/ HOLD#/
SIO2 SIO3
NC
NC
A
FIGURE 2-4:
TABLE 2-1:
Symbol
SCK
B
C
D
E
F
T4D-P1.0
PIN DESCRIPTION FOR 24-BALL TBGA
PIN DESCRIPTION
Pin Name
Serial Clock
Functions
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock
input, while output data is shifted out on the falling edge of the clock input.
To transfer commands, addresses, or data serially into the device or data out of
the device. Inputs are latched on the rising edge of the serial clock. Data is
shifted out on the falling edge of the serial clock. The Enable Quad I/O (EQIO)
command instruction configures these pins for Quad I/O mode.
To transfer commands, addresses or data serially into the device. Inputs are
latched on the rising edge of the serial clock. SI is the default state after a power
on reset.
To transfer data serially out of the device. Data is shifted out on the falling edge
of the serial clock. SO is the default state after a power on reset.
The device is enabled by a high to low transition on CE#. CE# must remain low
for the duration of any command sequence; or in the case of Write operations,
for the command/data input sequence.
The WP# is used in conjunction with the WPEN and IOC bits in the Configura-
tion register to prohibit write operations to the Block-Protection register. This pin
only works in SPI, single-bit and dual-bit Read mode.
Temporarily stops serial communication with the SPI Flash memory while the
device is selected. This pin only works in SPI, single-bit and dual-bit Read mode
and must be tied high when not in use.
To provide power supply voltage.
SIO[3:0]
Serial Data
Input/Output
SI
Serial Data Input
for SPI mode
Serial Data Output
for SPI mode
Chip Enable
SO
CE#
WP#
Write Protect
HOLD#
Hold
V
DD
V
SS
Power Supply
Ground
DS25119C-page 4
Advance Information
2013 Microchip Technology Inc.
NXP MCU
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