Note the following details of the code protection feature on Microchip devices:
•
•
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
•
•
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
K
EE
L
OQ
, K
EE
L
OQ
logo, MPLAB, PIC, PICmicro, PICSTART,
PIC
32
logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-670-8
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
®
MCUs and dsPIC
®
DSCs, K
EE
L
OQ
®
code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS39905E-page 2
2010 Microchip Technology Inc.
PIC24FJ256GA110 FAMILY
64/80/100-Pin, 16-Bit, General Purpose
Flash Microcontrollers with Peripheral Pin Select
Power Management:
• On-Chip 2.5V Voltage Regulator
• Switch between Clock Sources in Real Time
• Idle, Sleep and Doze modes with Fast Wake-up and
Two-Speed Start-up
• Run mode: 1 mA/MIPS, 2.0V Typical
• Standby Current with 32 kHz Oscillator: 2.6
A,
2.0V Typical
Peripheral Features:
• Peripheral Pin Select:
- Allows independent I/O mapping of many
peripherals at run time
- Continuous hardware integrity checking and safety
interlocks prevent unintentional configuration changes
- Up to 46 available pins (100-pin devices)
• Three 3-Wire/4-Wire SPI modules (supports
4 Frame modes) with 8-Level FIFO Buffer
• Three I
2
C™ modules support Multi-Master/Slave modes
and 7-Bit/10-Bit Addressing
• Four UART modules:
- Supports RS-485, RS-232, LIN/J2602 protocols
and IrDA
®
- On-chip hardware encoder/decoder for IrDA
- Auto-wake-up and Auto-Baud Detect (ABD)
- 4-level deep FIFO buffer
• Five 16-Bit Timers/Counters with Programmable Prescaler
• Nine 16-Bit Capture Inputs, each with a
Dedicated Time Base
• Nine 16-Bit Compare/PWM Outputs, each with a
Dedicated Time Base
• 8-Bit Parallel Master Port (PMP/PSP):
- Up to 16 address pins
- Programmable polarity on control lines
• Hardware Real-Time Clock/Calendar (RTCC):
- Provides clock, calendar and alarm functions
• Programmable Cyclic Redundancy Check (CRC) Generator
• Up to 5 External Interrupt Sources
High-Performance CPU:
Modified Harvard Architecture
Up to 16 MIPS Operation at 32 MHz
8 MHz Internal Oscillator
17-Bit x 17-Bit Single-Cycle Hardware Multiplier
32-Bit by 16-Bit Hardware Divider
16 x 16-Bit Working Register Array
C Compiler Optimized Instruction Set Architecture with
Flexible Addressing modes
• Linear Program Memory Addressing, Up to 12 Mbytes
• Linear Data Memory Addressing, Up to 64 Kbytes
• Two Address Generation Units for Separate Read and
Write Addressing of Data Memory
•
•
•
•
•
•
•
Analog Features:
• 10-Bit, Up to 16-Channel Analog-to-Digital (A/D)
Converter at 500 ksps:
- Conversions available in Sleep mode
• Three Analog Comparators with Programmable Input/
Output Configuration
• Charge Time Measurement Unit (CTMU)
Program
Memory (Bytes)
10-Bit A/D (ch)
SRAM (Bytes)
Remappable Peripherals
UART w/ IrDA
®
Capture Input
Timers 16-Bit
Compare/
PWM Output
Remappable
Pins
I
2
C™
Comparators
PMP/PSP
64GA106
128GA106
192GA106
256GA106
64GA108
128GA108
192GA108
256GA108
64GA110
128GA110
192GA110
256GA110
64
64
64
64
80
80
80
80
100
100
100
100
64K
128K
192K
256K
64K
128K
192K
256K
64K
128K
192K
256K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
31
31
31
31
42
42
42
42
46
46
46
46
5
5
5
5
5
5
5
5
5
5
5
5
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
4
4
4
4
4
4
4
4
4
4
4
4
SPI
PIC24FJ
Device
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
16
16
16
16
16
16
16
16
16
16
16
16
3
3
3
3
3
3
3
3
3
3
3
3
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
2010 Microchip Technology Inc.
DS39905E-page 3
CTMU
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
JTAG
Pins
PIC24FJ256GA110 FAMILY
Special Microcontroller Features:
•
•
•
•
•
•
Operating Voltage Range of 2.0V to 3.6V
Self-Reprogrammable under Software Control
5.5V Tolerant Input (digital pins only)
Configurable Open-Drain Outputs on Digital I/O
High-Current Sink/Source (18 mA/18 mA) on all I/O
Selectable Power Management modes:
- Sleep, Idle and Doze modes with fast wake-up
• Fail-Safe Clock Monitor Operation:
- Detects clock failure and switches to on-chip
FRC oscillator
• On-Chip LDO Regulator
• Power-on Reset (POR), Power-up Timer (PWRT),
Low-Voltage Detect (LVD) and Oscillator Start-up Timer
(OST)
• Flexible Watchdog Timer (WDT) with On-Chip
Low-Power RC Oscillator for Reliable Operation
• In-Circuit Serial Programming™ (ICSP™) and
In-Circuit Debug (ICD) via 2 Pins
• JTAG Boundary Scan Support
• Brown-out Reset (BOR)
• Flash Program Memory:
- 10,000 erase/write cycle endurance (minimum)
- 20-year data retention minimum
- Selectable write protection boundary
- Write protection option for Flash Configuration
Words
Pin Diagram (64-Pin TQFP and QFN
(1)
)
RP25/CN13/PMWR/RD4
52
C3INB/CN15/RD6
RP20/CN14/PMRD/RD5
54
53
RP22/CN52/PMBE/RD3
RP23/CN51/RD2
RP24/CN50/RD1
51
50
49
48
47
46
45
44
64
63
62
61
60
59
58
57
56
55
V
CAP
/V
DDCORE
C3INA/CN16/RD7
CN60/PMD2/RE2
CN59/PMD1/RE1
CN58/PMD0/RE0
CN69/RF1
CN62/PMD4/RE4
CN61/PMD3/RE3
CN68/RF0
ENVREG
CN63/PMD5/RE5
SCL3/CN64/PMD6/RE6
SDA3/CN65/PMD7/RE7
PMA5/RP21/C1IND/CN8/RG6
C1INC/RP26/CN9/PMA4/RG7
C2IND/RP19/CN10/PMA3/RG8
MCLR
C2INC/RP27/CN11/PMA2/RG9
V
SS
V
DD
PGEC3/AN5/C1INA/RP18/CN7/RB5
PGED3/AN4/C1INB/RP28/CN6/RB4
AN3/C2INA/CN5/RB3
AN2/C2INB/RP13/CN4/RB2
PGEC1/AN1/V
REF
-/RP1/CN3/RB1
PGED1/AN0/V
REF
+/RP0/CN2/PMA6/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SOSCO/C3INC/RPI37/T1CK/CN0/RC14
SOSCI/C3IND/CN1/RC13
RP11/CN49/RD0
RP12/CN56/PMCS1/RD11
RP3/CN55/PMCS2/RD10
RP4/CN54/RD9
RTCC/RP2/CN53/RD8
V
SS
OSCO/CLKO/CN22/RC15
OSCI/CLKI/CN23/RC12
V
DD
SCL1/CN83/RG2
SDA1/CN84/RG3
ASCK1/RPI45/INT0/CN72/RF6
RP30/CN70/RF2
RP16/CN71/RF3
PIC24FJ64GA106
PIC24FJ128GA106
PIC24FJ192GA106
PIC24FJ256GA106
43
42
41
40
39
38
37
36
35
34
33
AV
DD
V
DD
TDI/PMA10/AN13/CTED1/CN31/RB13
SDA2/RP10/CN17/PMA9/RF4
TMS/AN10/CV
REF
/CN28/PMA13/RB10
TDO/AN11/CN29/PMA12/RB11
V
SS
TCK/AN12/CTED2/CN30/PMA11/RB12
AN14/CTPLS/RP14/CN32/PMA1/RB14
Legend:
Note 1:
Shaded pins
indicate pins tolerant to up to +5.5 V
DC
.
RPn
represents remappable pins for Peripheral Pin Select (PPS) feature.
For QFN devices, the backplane on the underside of the device must also be connected to V
SS
.
AN15/REFO/RP29/CN12/PMA0/RB15
SCL2/RP17/CN18/PMA8/RF5
PGED2/AN7/RP7/CN25/RB7
PGEC2/AN6/RP6/CN24/RB6
AV
SS
AN8/RP8/CN26/RB8
AN9/RP9/CN27/PMA7/RB9
DS39905E-page 4
2010 Microchip Technology Inc.
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