Supertex inc.
MD1822
High Speed Four Channel MOSFET Driver with Two Inverting
and Two Non-Inverting Outputs
►
Mixed inversion MOSFET driver
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6.0ns rise and fall time
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2.0A peak output source/sink current
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1.8 to 5.0V input CMOS compatible
5.0 to 10V total supply voltage
Smart logic threshold
Low jitter design
Features
General Description
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Four matched channels
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Drives two P- and two N-channel MOSFETs
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Outputs can swing below ground
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Low inductance, quad flat no-lead package
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High performance, thermally enhanced
packaging
The Supertex MD1822 is a high speed, four channel MOSFET driver
designed to drive high voltage P- and N-channel MOSFETs for medical
ultrasound applications and other applications requiring a high output
current for a capacitive load. The high-speed input stage of the MD1822
can operate from a 1.8 to 5.0V logic interface with an optimum operating
input signal range of 1.8 to 3.3V. An adaptive threshold circuit is used to
set the level translator switch threshold to the average of the input logic 0
and logic 1 levels. The input logic levels may be ground referenced, even
though the driver is putting out bipolar signals. The level translator uses a
proprietary circuit, which provides DC coupling together with high-speed
operation.
The output stage of the MD1822 has separate power connections
enabling the output signal L and H levels to be chosen independently from
the supply voltages used for the majority of the circuit. As an example, the
input logic levels may be 0 and 1.8V, the control logic may be powered by
+5.0 and -5.0V, and the output L and H levels may be varied anywhere
over the range of -5.0 to +5.0V. The output stage is capable of peak
currents of up to ±2.0A, depending on the supply voltages used and load
capacitance present. The PE pin serves a dual purpose. First, its logic H
level is used to compute the threshold voltage level for the channel input
level translators. Second, when PE is low, the outputs are disabled, with
the A & C output high and the B & D output low. This assists in properly
precharging the AC coupling capacitors that may be used in series in the
gate drive circuit of an external PMOS and NMOS transistor pair.
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Applications
Medical ultrasound imaging
Piezoelectric transducer drivers
Non-Destructive Testing (NDT)
PIN diode driver
CCD Clock driver/buffer
High speed level translator
Typical Application Circuit
0.1µF
+10V
+10V
+100V
+3.3V
PE
PIN
3.3V CMOS
Logic Inputs
Supertex
MD1822
VDD
VH
OUTA
OUTB
0.47µF
0.47µF
10nF
INA
INB
10nF
-100V
NIN
0.47µF
OUTC
DMP
INC
Supertex
TC6320
HV
OUT
IND
GND
VSS
OUTD
VL
10nF
10nF
Supertex
TC6320
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
MD1822
Ordering Information
Device
MD1822
3.00x3.00mm body
1.00mm height (max)
0.50mm pitch
16-Lead QFN
MD1822K6-G
-G indicates package is RoHS compliant (‘Green’)
Absolute Maximum Ratings
Parameter
V
DD
-V
SS
, Logic supply voltage
V
H
, Output high supply voltage
V
L
, Output low supply voltage
V
SS
, Low side supply voltage
Logic input levels
Maximum junction temperature
Storage temperature
Operating temperature
Package power dissipation
Thermal resistance (θ
JA
)*
Value
-0.5V to +12.5V
V
L
- 0.5V to V
DD
+0.5V
V
SS
- 0.5V to V
H
+0.5V
-6.0V to +0.5V
V
SS
- 0.5V to GND +5.5V
+125°C
-65°C to 150°C
-20°C to +85°C
2.2W
55°C/W
Pin Configuration
16
1
16-Lead QFN (K6)
(top view)
Product Marking
1822
YWLL
Y = Last Digit of Year Sealed
W = Code for Week Sealed
L = Lot Number
= “Green” Packaging
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
* 1.0oz 4-layer 3x4” PCB
Package may or may not include the following marks: Si or
16-Lead QFN (K6)
DC Electrical Characteristics
(V
Sym
V
DD
- V
SS
V
SS
V
H
V
L
I
DDQ
I
HQ
I
DDQ
I
HQ
I
DD
I
H
V
IH
V
IL
I
IH
I
IL
V
IH
V
IL
R
IN_PE
Parameter
Logic supply voltage
Low side supply voltage
Output high supply voltage
Output low supply voltage
V
DD
quiescent current
V
H
quiescent current
V
DD
quiescent current
V
H
quiescent current
V
DD
average current
V
H
average current
Input logic voltage high
Input logic voltage low
Input logic current high
Input logic current low
PE input logic voltage high
PE input logic voltage low
PE input impedance to GND
H
= V
DD
= 10V, V
L
= V
SS
= GND = 0V, V
PE
= 3.3V, T
A
= 25°C)
Min
4.75
-5.5
V
SS
+2.0
V
SS
-
-
-
-
-
-
V
PE
-0.3
0
-
-
1.70
0
100
Typ
-
-
-
-
60
2.0
1.0
2.0
4.0
10
-
-
-
3.30
-
-
Max
11.5
0
V
DD
V
DD
-4.0
-
-
-
-
-
-
V
PE
0.3
1.0
1.0
5.25
0.3
-
Units
V
V
V
V
µA
µA
mA
µA
mA
mA
V
V
µA
µA
V
V
KΩ
Conditions
4.0V ≤ V
DD
≤11.5V
---
---
---
No input transitions, PE = 0
No input transitions, PE = 1
One channel on at 5.0Mhz,
No load
For logic inputs INA, INB, INC,
and IND
For logic input PE
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
2
Tel: 408-222-8888
www.supertex.com
MD1822
DC Electrical Characteristics
(cont.)
(V
Sym
C
IN
R
SINK
R
SOURCE
I
SINK
I
SOURCE
Parameter
Logic input capacitance
Output sink resistance
Output source resistance
Peak output sink current
Peak output source current
H
H
= V
DD
= 10V, V
L
= V
SS
= GND = 0V, V
PE
= 3.3V, T
A
= 25°C)
Min
-
-
-
-
-
Typ
5.0
1.5
2.0
2.0
2.0
Max
10
-
-
-
-
Units
pF
Ω
Ω
A
A
Conditions
---
I
SINK
= 50mA
I
SOURCE
= 50mA
---
---
AC Electrical Characteristics
(V
Sym
t
irf
t
PLH
t
PHL
t
r
t
f
l t
r
- t
f
l
l t
PLH
-t
PHL
l
∆t
dm
t
PE-ON
t
PE-OFF
Parameter
Input or PE rise & fall time
Propagation delay when output
is from low to high
Propagation delay when output
is from high to low
Output rise time
Output fall time
Rise and fall time matching
Propagation low to high and
high to low matching
Propagation delay matching
PE on-time
PE off-time
= V
DD
= 10V, V
L
= V
SS
= GND = 0V, V
PE
= 3.3V, T
A
= 25°C)
Min
-
-
-
-
-
-
-
-
-
-
Typ
-
6.5
6.5
7.0
7.0
1.0
1.0
±2.0
-
-
Max
10
-
-
-
-
-
-
-
5.0
4.0
Units
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
Conditions
Logic input edge speed
requirement
C
LOAD
= 1000pF, see timing
diagram
Input signal rise/fall time 2.0ns
For each channel
Device to device delay match
V
PE
= 1.7 ~ 5.25V
V
DD
= 7.5 ~ 11.5V
-20 ~ 85
O
C
Logic Truth Table
Logic Inputs
PE
H
H
H
H
L
PE
H
H
H
H
L
INA
L
L
H
H
X
INC
L
L
H
H
X
INB
H
L
H
L
X
IND
H
L
H
L
X
OUTA
V
H
V
H
V
L
V
L
V
H
OUTC
V
H
V
H
V
L
V
L
V
H
Output
OUTB
V
H
V
L
V
H
V
L
V
L
OUTD
V
H
V
L
V
H
V
L
V
L
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
3
Tel: 408-222-8888
www.supertex.com
MD1822
Simplified Block Diagram
MD1822
PE
INA
VDD
VH
OUTA
INB
OUTB
INC
OUTC
IND
GND
VSS
VL
OUTD
Detailed Block Diagram
PE
INA
MD1822
Level
Shifter
Level
Shifter
VDD
VH
OUTA
VSS
VDD
VL
VH
INB
Level
Shifter
OUTB
VSS
VDD
VL
VH
INC
Level
Shifter
OUTC
VSS
VDD
VL
VH
IND
Level
Shifter
OUTD
SUB
GND
VSS
VL
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
4
Tel: 408-222-8888
www.supertex.com
MD1822
Timing Diagram
V
TH
/ V
PE
Curve
V
TH
vs V
PE
3.3V
IN
0V
t
PLH
10V
OUT
0V
10%
t
r
t
f
90%
t
PHL
90%
10%
V
TH
1.0
0.5
0
50%
50%
V
PE
/2
2.0
1.5
0
1.0
2.0
V
PE
3.0
4.0
5.0
Application Information
For proper operation of the MD1822, low inductance bypass
capacitors should be used on the various supply pins. The
GND pin should be connected to the logic ground. The INA,
INB, INC, IND, and PE pins should be connected to a logic
source with a swing of GND to PE, where PE is 1.8 to 5.0V.
Good trace practices should be followed corresponding to
the desired operating speed. The internal circuitry of the
MD1822 is capable of operating up to 100MHz, with the
primary speed limitation being the loading effects of the load
capacitance. Because of this speed and the high transient
currents that result with capacitive loads, the bypass
capacitors should be as close to the chip pins as possible.
Unless the load specifically requires bipolar drive, the VSS
and VL pins should have low inductance feed-through
connections directly to a ground plane. If these voltages
are not zero, then they need bypass capacitors in a manner
similar to the positive power supplies. The power connection
VDD should have a ceramic bypass capacitor to the ground
plane with short leads and decoupling components to prevent
resonance in the powerleads.
The voltages of VH and VL decide the output signal levels.
These two pins can draw fast transient currents of up to
2.0A, so they should be provided with an appropriate bypass
capacitor located next to the chip pins. A ceramic capacitor
of up to 1.0µF may be appropriate, with a series ferrite bead
to prevent resonance in the power supply lead coming to
the capacitor. Pay particular attention to minimizing trace
lengths, current loop area and using sufficient trace width to
reduce inductance. Surface mount components are highly
recommended. Since the output impedance of this driver is
very low, in some cases it may be desirable to add a small
series resistance in series with the output signal to obtain
better waveform transitions at the load terminals. This will of
course reduce the output voltage slew rate at the terminals
of a capacitive load.
Pay particular attention that parasitic couplings are minimized
from the output to the input signal terminals. The parasitic
feedback may cause oscillations or spurious waveform
shapes on the edges of signal transitions. Since the input
operates with signals down to 1.8V even small coupled
voltages may cause problems. Use of a solid ground plane
and good power and signal layout practices will prevent this
problem. Be careful that a circulating ground return current
from a capacitive load cannot react with common inductance
to cause noise voltages in the input logic circuitry.
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
5
Tel: 408-222-8888
www.supertex.com
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