M88 FAMILY
In-System Programmable (ISP)
Multiple-Memory and Logic FLASH+PSD Systems for MCUs
PRELIMINARY DATA
s
s
s
s
s
s
s
s
s
s
Single Supply Voltage:
– 5 V±10% for M88x3FxY
– 3 V (+20/–10%) for M88x3FxW
Fast Access Time:
– 90 ns or 150 ns at 5 V
– 150 ns at 3 V
1 Mbit (128K x 8) Flash memory
– 8 uniform blocks of 16K x 8 each
A second non-volatile memory:
– 256 Kbit (32K x 8) EEPROM (for M8813F1x)
or Flash memory (for M88x3F2x)
– 4 uniform blocks
16 Kbit (2K x 8) SRAM for M8813Fxx (not
available on M8803Fxx)
Over 3,000 Gates of PLD
Reconfigurable I/O ports
JTAG Interface
Programmable power management
High Endurance:
– 100,000 Erase/Write Cycles of Flash Memory
– 10,000 Erase/Write Cycles of EEPROM
– 1,000 Erase/Write Cycles of PLD
PQFP52 (T)
PLCC52 (K)
Figure 1. Logic Diagram
VCC
Table 1. Signal Names
PA0-PA7
PB0-PB7
PC0-PC7
PC2 = Voltage Stand-by
PD0-PD2
AD0-AD15
CNTL0-CNTL2
CNTL1 = CLOCK IN
RESET
V
CC
V
SS
Reset
Supply Voltage
Ground
Port-D Data Lines
Address/Data Lines
Control Lines
Port-A Data Lines
Port-B Data Lines
Port-C Data Lines
8
PA0-PA7
3
CNTL0-
CNTL2
16
AD0-AD15
3
RESET
PD0-PD2
FLASH+PSD
8
PC0-PC7
8
PB0-PB7
VSS
AI02856
January 2000
1/85
M88 FAMILY
Figure 2A. PLCC Connections
CNTL1
CNTL2
RESET
CNTL0
PB0
PB1
PB2
PB3
PB4
PB5
GND
PB6
PB7
Figure 2B. PQFP Connections
PD2
PD1
PD0
PC7
PC6
PC5
PC4
VCC
GND
PC3
PC2
PC1
PC0
8
9
10
11
12
13
14
15
16
17
18
19
20
46
45
44
43
42
41
40
39
38
37
36
35
34
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
V CC
AD7
AD6
AD5
AD4
PA7 14
PA6 15
PA5 16
PA4 17
PA3 18
GND 19
PA2 20
PA1 21
PA0 22
AD0 23
AD1 24
AD2 25
AD3 26
PD2 1
PD1 2
PD0 3
PC7 4
PC6 5
PC5 6
PC4 7
V
CC
8
GND 9
PC3 10
PC2 11
PC1 12
PC0 13
39 AD15
38 AD14
37 AD13
36 AD12
35 AD11
34 AD10
33 AD9
32 AD8
31 V
CC
30 AD7
29 AD6
28 AD5
27 AD4
21
22
23
24
25
26
27
28
29
30
31
32
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
33
40 CNTLO
41 RESET
43 CNTL1
42 CNTL2
46 GND
52 PB0
51 PB1
50 PB2
49 PB3
48 PB4
47 PB5
45 PB6
44 PB7
AD1
AD2
GND
AD0
AD3
DESCRIPTION
The M88x3Fxx FLASH+PSD family of memory
systems for microcontrollers (MCUs) brings In-
System-Programmability (ISP) to Flash memory
and programmable logic. The result is a simple
and flexible solution for embedded designs.
M88x3Fxx FLASH+PSD devices combine many of
the peripheral functions found in MCU based
applications.
M88x3Fxx FLASH+PSD devices feature an
optimized “microcontroller macrocell” logic
architecture called the Macrocell. The Macrocell
was created to address the unique requirements
of embedded system designs. It allows direct
Table 2. Product Range
1
Part Number
M813F1Y
M813F2Y
M813F3Y
M803F2Y
M803F3Y
M813F1W
M813F2W
M813F3W
M803F2W
M803F3W
16 Kbit
16 Kbit
16 Kbit
SRAM
2
Flash Program Store I/O Ports 2nd NVM (Boot Area) Voltage Range
16 Kbit
16 Kbit
16 Kbit
1 Mbit
1 Mbit
1 Mbit
1 Mbit
1 Mbit
1 Mbit
1 Mbit
1 Mbit
1 Mbit
1 Mbit
27
27
27
27
27
27
27
27
27
27
256 Kbit Flash
256 Kbit EEPROM
256 Kbit Flash
2.7-3.6 V
150 ns
256 Kbit Flash
256 Kbit EEPROM
256 Kbit Flash
4.5-5.5 V
90 ns or
150 ns
Access Time
Note: 1. All products support: JTAG Serial ISP, MCU Parallel ISP, ISP Flash memory, ISP CPLD, Security features, Power Management
Unit (PMU), Automatic Power Down (APD)
2. All devices with SRAM may be backed up using an external battery.
7
5
4
3
2
52
51
50
49
48
47
6
1
AI02858
AI02857
connection between the system address/data bus,
and the internal PSD registers, to simplify
communication between the MCU and other
supporting devices.
The M88x3Fxx FLASH+PSD family includes a
JTAG serial programming interface, to allow in-
system-programming of the entire device. This
feature reduces development time, simplifies the
manufacturing flow, and dramatically lowers the
cost of field upgrades. Using ST’s special Fast-
JTAG programming, a design can be rapidly
programmed into the M88x3Fxx FLASH+PSD.
The innovative M88x3Fxx FLASH+PSD family
solves key problems faced by designers when
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VSTDBY/I/O
MCU Address / Data / Control Bus
8
PMU
(PC2)
Page Reg
FLASH Memory
Sector
Select
Eight Blocks
1Mbits Total
Programmable
I/O PORT
Programmable
I/O PORT
Embedded Algorithm
Command Registers
MCU
Address/Data
AD0-AD7
A8-A15
PA0-PA7
Decode PLD
Boot
PLD INPUT BUS
FLASH or EEPROM
Four Sectors
256 Kbits Total
73
Control
RD/ WR/
SRAM
MCU
Control Interface
Figure 3. M88x3Fxx FLASH+PSD Block Diagram
Periph. +
I/O Sel
PB0-PB7
ISP LOADER
Configuration, PLD,
& FLASH Memory
JTAG Serial Channel
Scratch Pad
16 Kbits
SRAM
Direct Read & Write Of Macrocell
ISP CPLD
73
PT
Alloc.
24 Input Macrocell (Port A,B,C)
16 Output Macrocell
16
Macrocell
Alloc.
I/O Ports
CLKIN/PD1
3 CS
Programmable
I/O PORT
Programmable
I/O PORT
(PC0-PC1), (PC3-PC6)
PD0-PD2
PC0-PC7
Device
Security
Direct Read of Macrocell
Output Macrocell Feedback,
Input Macrocell & Input Ports
AI02861C
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M88 FAMILY
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M88 FAMILY
Table 3. Absolute Maximum Ratings
1
Symbol
T
A
T
STG
T
LEAD
V
CC
V
PP
V
IO
V
ESD
Parameter
Industrial
Ambient Operating Temperature
Commercial
Storage Temperature
Lead Temperature during Soldering
Supply Voltage
Device Programmer Supply Voltage
Input or Output range (Q = V
OH
or Hi-Z)
Electrostatic Discharge Voltage (Human Body model)
2
0 to 70
-65 to 125
t.b.c.
–0.6 to 7
3
–0.6 to 14
3
–0.6 to 7
3
2000
Value
-40 to 85
Unit
°C
°C
°C
°C
V
V
V
V
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. MIL-STD-883C, 3015.7 (100 pF, 1500
Ω)
3. For the M88x3FxY, 5 V range only.
managing discrete Flash memory devices, such
as:
– In-system first-time programming
– Complex address decoding
– Concurrent Flash or EEPROM programming.
The M88x3Fxx FLASH+PSD’s serial JTAG
interface allows in-system-programming and
eliminates the need for a boot EPROM or Flash
memory, or an external programmer. To simplify
Flash memory updates, some members of the
family perform program execution out of a
secondary EEPROM (for the M8813F1x) or Flash
memory (for the M88x3F2x) while the main Flash
memory is being updated. This solution avoids the
complicated hardware and software overhead
necessary to implement in-system Flash memory
updates.
ST makes available a software development tool,
PSDsoft, that generates ANSI-C compliant code
for use with your target MCU. This code allows you
to manipulate the non-volatile memory (NVM)
within the PSD. Code examples are also provided
for:
– Flash memory ISP via the UART of the host
MCU
– Memory paging to execute code across several
PSD memory pages
– Loading, reading, and manipulation of PSD
Macrocells by the MCU.
KEY FEATURES
s
A simple interface to 8-bit microcontrollers,
without the need for external glue-logic. The bus
interface logic uses the control signals
generated by the microcontroller when the
address is decoded and a read or write is
performed. The MCU families supported
include:
– Intel 8031, 80196, 80186, 80C251, and
80386EX
– Motorola 68HC11, 68HC16, 68HC12, and
683XX
– Philips 8031 and 8051XA
– Zilog Z80 and Z8
– NEURON
®
3150 CHIP™.
Internal 1 Mbit (128K x 8) Flash memory. This is
the main Flash memory. It is divided into eight
equal-sized blocks that can be accessed with
user-specified addresses.
Optional internal secondary 256 Kbit (32K x 8)
EEPROM or Flash boot memory. This is divided
into four equal-sized blocks that can be
accessed with user-specified addresses. The
main Flash memory can be updated
concurrently while the secondary memory is
executing code.
Optional 16 Kbit (2K x 8) scratch-pad SRAM. Its
contents can be protected from a power failure
by connecting an external battery.
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M88 FAMILY
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Optional 64 byte One Time Programmable
(OTP) memory (on the M8813F1x) that can be
used for product configuration and calibration.
CPLD with 16 Output Macrocells (OMCs) and
24 Input Macrocells (IMCs). The CPLD may be
used to implement efficiently a variety of logic
functions for internal and external control.
Examples include state machines, loadable
shift registers, and loadable counters.
Decode PLD (DPLD) that decodes address for
selection of internal memory blocks. The DPLD
can also be used to generate external chip
selects.
27 individually configurable I/O port pins that
can be used for the following functions:
MCU I/Os
PLD I/Os
Latched MCU address output
Special function I/Os
16 of the I/O ports may be configured as
open-drain outputs.
Stand-by current as low as 50
µA
for 5 V
devices, 25
µA
for 3 V devices.
Built-in JTAG compliant serial port allows full-
chip In-System Programmability (ISP). With it,
you can program a blank device or reprogram a
device in the factory or the field.
Internal page register that can be used to
expand the microcontroller address space by a
factor of 256.
Internal programmable Power Management
Unit (PMU) that supports a low power mode
called Power Down Mode. The PMU can
automatically detect a lack of microcontroller
activity and put the M88x3Fxx FLASH+PSD into
Power Down Mode.
–
–
–
–
–
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M88X3FXX FLASH+PSD FAMILY
All M88x3Fxx FLASH+PSD devices provide the
base features: 1 Mbit main Flash Memory, JTAG
port, CPLD, DPLD, power management, and
twenty-seven I/O pins. Some of the members of
the M88x3Fxx FLASH+PSD family add to this set
of basic features:
s
M8813Fxx adds 16 Kbit (2K x 8) SRAM to the
base feature set.
s
s
M8813F1x adds 256 Kbit (32K x 8) EEPROM to
the base feature set. It also adds 64 bytes of
OTP memory for any use (product serial
number, calibration constants, etc.). Once
written, the OTP memory can never be altered.
M88x3F2x adds a secondary 256 Kbit (32K x 8)
Flash memory to the base feature set.
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These independent memories can operate
concurrently with each other and with the main
Flash memory.
Table 2 summarizes all the devices in the
M88x3Fxx FLASH+PSD family.
M88X3FXX FLASH+PSD ARCHITECTURAL
OVERVIEW
M88x3Fxx FLASH+PSD devices contain several
major functional blocks. Figure 3 shows the
architecture of the M88x3Fxx FLASH+PSD device
family. The functions of each block are described
briefly in the following sections. Many of the blocks
perform multiple functions and are user
configurable.
Memory
Each of the memories is briefly discussed in the
following paragraphs. A more detailed discussion
can be found in the section entitled “M88 Family
Functional Blocks”, on page 12.
The 1 Mbit (128K x 8) Flash memory is the main
memory of the M88x3Fxx FLASH+PSD. It is
divided into eight equally-sized blocks that are
individually selectable.
The optional 256 Kbit (32K x 8) EEPROM or Flash
memory is divided into four equally-sized blocks.
Each block is individually selectable.
The optional 16 Kbit (2K x 8) SRAM is intended for
use as a scratch-pad memory or as an extension
to the microcontroller SRAM. If an external battery
is connected to the M88x3Fxx FLASH+PSD’s
VSTBY pin, data will be retained in the event of a
power failure.
Each block of memory can be located in a different
address space as defined by the user. The access
times for all memory types includes the address
latching and DPLD decoding time.
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GENERAL INFORMATION
The M88x3Fxx FLASH+PSD architecture allows
In-System Programming of all Memory, PLD Logic
and Device Configuration. The embedded Input
and
Output
Macrocells
enable
efficient
implementation of user defined logic functions that
require both software and hardware interaction.
The devices eliminate the need for discrete ‘glue’
logic, and allow the development of entire systems
using only a few highly integrated devices.
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