Ultra Series
™
Crystal Oscillator
Si564 Data Sheet
Ultra Low Jitter I2C Programmable XO (90 fs), 0.2 to
3000 MHz
The Si564 Ultra Series
™
oscillator utilizes Silicon Laboratories’ advanced 4
th
generation DSPLL
®
technology to provide an ultra-low jitter, low phase noise
clock at any output frequency. The device is user-programmed via simple
I2C commands to provide any frequency from 0.2 to 3000 MHz with <1 ppb
resolution and maintains exceptionally low jitter for both integer and fraction-
al frequencies across its operating range. The Si564 offers excellent reliabili-
ty and frequency stability as well as guaranteed aging performance. On-chip
power supply filtering provides industry-leading power supply noise rejection,
simplifying the task of generating low jitter clocks in noisy systems that use
switched-mode power supplies. The Si564 has a dramatically simplified sup-
ply chain that enables Silicon Labs to ship custom frequency samples 1-2
weeks after receipt of order. Unlike a traditional XO, where a different crystal
is required for each output frequency, the Si564 uses one simple crystal and
a DSPLL IC-based approach to provide the desired output frequency. The
Si564 is factory-configurable for a wide variety of user specifications, includ-
ing startup frequency, I2C address, output format, and OE pin location/
polarity. Specific configurations are factory-programmed at time of shipment,
eliminating the long lead times associated with custom oscillators.
Pin Assignments
SDA
OE/FS/NC
1
7
6
VDD
KEY FEATURES
• I2C programmable to any frequency from 0.2 to
3000 MHz with < 1 ppb resolution
• Ultra low jitter: 90 fs RMS Typ (12 kHz – 20 MHz)
• Configure up to 4 pin-selectable startup frequencies
• I2C interface supports 100 kbps, 400 kbps, and 1
Mbps (Fast Mode Plus)
• Excellent PSRR and supply noise immunity: –80
dBc Typ
• 3.3 V, 2.5 V and 1.8 V V
DD
supply operation from
the same part number
• LVPECL, LVDS, CML, HCSL, CMOS, and Dual
CMOS output options
• 3.2x5, 5x7 mm package footprints
• Samples available with 1-2 week lead times
APPLICATIONS
• 100G/200G/400G OTN, coherent optics, PAM4
• 10G/40G/100G optical ethernet
• 3G-SDI/12G-SDI/24G-SDI broadcast video
• Servers, switches, storage, search acceleration
• Test and measurement
• FPGA/ASIC clocking
NC/OE/FS
GND
2
3
8
SCL
(Top View)
5
4
CLK–
CLK+
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Pin #
1, 2
3
4
5
6
7
8
Descriptions
Selectable via ordering option
OE = Output enable; FS = Frequency Select; NC = No connect
GND = Ground
CLK+ = Clock output
CLK- = Complementary clock output. Not used for CMOS.
VDD = Power supply
SDA = I2C Serial Data
SCL = I2C Serial Clock
NVM
Control
OSC
Fixed
Frequency
Crystal
Frequency
Flexible
DSPLL
DCO
Low
Noise
Driver
Digital
Phase
Detector
Phase Error
Cancellation
Phase Error
Fractional
Divider
Digital
Loop
Filter
Flexible
Formats,
1.8V – 3.3V
Operation
Power Supply Regulation
OE, Frequency Select
(I2C and Pin Control)
Built-in Power Supply
Noise Rejection
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Rev. 1.0
Si564 Data Sheet
Ordering Guide
1. Ordering Guide
The Si564 XO supports a variety of options including startup frequency, output format, and OE pin location/polarity, as shown in the
chart below. Specific device configurations are programmed into the part at time of shipment, and samples are available in 1-2 weeks.
Silicon Laboratories provides an online part number configuration utility to simplify this process. Refer to
www.silabs.com/oscillators
to
access this tool and for further ordering instructions.
XO Series
564
Description
I2C Oscillator
Temp Stability
A
Total Stability
2
Package
5x7 mm
3.2x5 mm
Temperature Grade
-40 to 85 °C
±
20 ppm
±
50 ppm
A
B
G
564
A
A
A
A
-
-
-
-
-
-
A
B
G
R
Device Revision
Signal Format
LVPECL
LVDS
CMOS
CML
HCSL
Dual CMOS
(In-Phase)
Dual CMOS
(Complementary)
Custom
1
Order
Option
2.5, 3.3 V
A
1.8, 2.5, 3.3 V
B
1.8, 2.5, 3.3 V
C
1.8, 2.5, 3.3 V
D
VDD Range
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
E
F
Code
G
X
A
B
C
D
E
F
G
H
J
OE Pin
Pin 1
Pin 1
Pin 2
Pin 2
Pin 1
Pin 1
Pin 2
Pin 2
--
Code
A
B
C
D
Supported Frequency Range
0.2-3000 MHz
0.2-1500 MHz
0.2-800 MHz
0.2-325 MHz (CMOS available to 250 MHz)
Pinout Option
OE Polarity
Active High
Active Low
Active High
Active Low
Active High
Active Low
Active High
Active Low
--
FS0
(Dual)
--
--
--
--
Pin 2
Pin 2
Pin 1
Pin 1
Pin 1
FS1
(Quad)
--
--
--
--
--
--
--
--
Pin 2
Frequency
Code
3
Code
R
<Blank>
Reel
Tape and Reel
Coil Tape
Description
The Si564 supports one,
two, or four user-defined
startup frequencies in the
range selected by the
Supported Frequency
Range code. A user-
defined 7-bit I2C address
is supported. Each unique
startup configuration and
I2C address combination
is assigned a 6-digit code.
xxxxxx
Single
Codes A, B
SDA
OE
NC
GND
1
2
3
7
6
5
4
VDD
CLK–
CLK+
OE
FS0
GND
1
2
3
Dual
Codes E, F
SDA
7
6
5
4
VDD
CLK–
CLK+
FS0
FS1
GND
1
2
3
Quad
Code J
SDA
7
6
5
4
VDD
CLK–
CLK+
8
SCL
8
SCL
8
SCL
Codes C, D
SDA
NC
OE
GND
1
2
3
7
6
5
4
VDD
CLK–
CLK+
FS0
OE
GND
Codes G, H
SDA
1
2
3
7
6
5
4
VDD
CLK–
CLK+
8
SCL
8
SCL
If replacing Si570A-K, use Code C
If replacing Si570M-W, use Code D
Notes:
1. Contact Silicon Labs for non-standard configurations.
2. Total stability includes temp stability, initial accuracy, load pulling, VDD variation, and 20 year aging at 70 °C.
3. Create custom part numbers at
www.silabs.com/oscillators.
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Rev. 1.0 | 3
Si564 Data Sheet
Ordering Guide
1.1 Technical Support
Frequently Asked Questions (FAQ)
Oscillator Phase Noise Lookup Utility
Quality and Reliability
Development Kits
www.silabs.com/Si564-FAQ
www.silabs.com/oscillator-phase-noise-lookup
www.silabs.com/quality
www.silabs.com/oscillator-tools
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Si564 Data Sheet
Electrical Specifications
2. Electrical Specifications
Table 2.1. Electrical Specifications
V
DD
= 1.8 V, 2.5 or 3.3 V ± 5%, T
A
= –40 to 85 ºC
Parameter
Temperature Range
Frequency Range
Symbol
T
A
F
CLK
LVPECL, LVDS, CML
HCSL
CMOS, Dual CMOS
Supply Voltage
V
DD
3.3 V
2.5 V
1.8 V
Supply Current
I
DD
LVPECL (output enabled)
LVDS/CML (output enabled)
HCSL (output enabled)
CMOS (output enabled)
Dual CMOS (output enabled)
Tristate Hi-Z (output disabled)
Temperature Stability
Total Stability
1
Rise/Fall Time
(20% to 80% V
PP
)
F
STAB
T
R
/T
F
Frequency stability Grade A
Frequency stability Grade A
LVPECL/LVDS/CML
CMOS / Dual CMOS
(C
L
= 5 pF)
HCSL, F
CLK
>50 MHz
Duty Cycle
Output Enable (OE),
Frequency Select (FS0, FS1)
2
D
C
V
IH
V
IL
T
D
T
E
T
FS
Powerup Time
LVPECL Output Option
3
t
OSC
V
OC
V
O
Output Disable Time, F
CLK
>10 MHz
Output Enable Time, F
CLK
>10 MHz
Settling Time after FS Change
Time from 0.9 × V
DD
until output fre-
quency (F
CLK
) within spec
Mid-level
Swing (diff, F
CLK
< 1.5 GHz)
Swing (diff, F
CLK
> 1.5 GHz)
6
All formats
Test Condition/Comment
Min
–40
0.2
0.2
0.2
3.135
2.375
1.71
—
—
—
—
—
—
–20
–50
—
—
—
45
0.7 × V
DD
—
—
—
—
—
V
DD
– 1.42
1.1
0.55
Typ
—
—
—
—
3.3
2.5
1.8
110
90
85
85
95
73
—
—
—
0.5
—
—
—
—
—
—
—
—
—
—
—
Max
85
3000
400
250
3.465
2.625
1.89
160
157
130
135
145
—
20
50
350
1.5
550
55
—
0.3 × V
DD
3
20
10
10
V
DD
– 1.25
1.9
1.7
Unit
ºC
MHz
MHz
MHz
V
V
V
mA
mA
mA
mA
mA
mA
ppm
ppm
ps
ns
ps
%
V
V
µs
µs
ms
ms
V
V
PP
V
PP
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