R O C K W E L L
S E M I C O N D U C T O R
S Y S T E M S
Network
access
RS8228
Octal ATM Transmission
datasheett
Convergence PHY Device
PROVIDING
HIGH
SPEED
MULTIMEDIA
CONNECTIONS
September 1998
Advance Information
This document contains information on a product under development. The parametric information contains target
parameters that are subject to change.
RS8228
Octal ATM Transmission Convergence PHY Device
The RS8228 Octal ATM Transmission Convergence PHY device dramatically
improves performance for switch and access system low-speed ports by integrating
all of the ATM physical layer processing functions found in the ATM Forum Cell Based
Transmission Convergence Sublayer specification (af-phy-0043.000) for eight indi-
vidual ports. Each port can be independently configured for operation at speeds
ranging from 64 kbps to 52 Mbps. There is also a powerdown mode option for each
TC port. A UTOPIA Level 2 Multi-PHY interface connects the device to the host switch
or terminal system and concentrates the ATM cell traffic onto one interface.
Typical system implementations center around the concentration of ATM cells
over standard PDH data rates such as T1/E1 lines, DS3 lines, and multiple Digital
Subscriber Line (DSL) formats such as HDSL, ADSL or VDSL*. For each format,
external devices perform the appropriate Physical Media Dependent (PMD) layer
functions and present the RS8228 with a payload bit stream. The RS8228 then per-
forms all cell-alignment functions on that bit stream. This gives system designers a
simple, modular, and low-cost architecture for supporting all UNI and NNI ATM inter-
faces below 52 Mbps. Since the RS8228 performs only the cell-based portion of the
protocol stack, designers can select the most integrated framer and Line Interface
Unit (LIU) available or reuse existing devices and software.
The RS8228 can also be used in combination with a Rockwell Segmentation and
Reassembly (SAR) device. The RS8228 gluelessly connects to the SAR via the UTO-
PIA and microprocessor interfaces. The device can be configured and controlled
optionally through a generic microprocessor interface. The RS8228’s chip-select fea-
ture allows the microprocessor to select any of the framers through the PHY. The
RS8228’s eight interrupt inputs provide an internal mechanism for registering and
controlling generated interrupts.
* The term xDSL is used throughout this document to refer to the various DSL formats as a
group.
Distinguishing Features
•
•
8 Cell-based TC Ports
UTOPIA Interface
– Level 2
– 8/16 bit modes
– Multi-PHY
– Redundant channel
Glueless interface to:
– Bt8370 T1/E1 Framer
– Bt8330 DS3 Framer
– Rockwell HDSL Devices
– Bt8233/RS8234 SAR
Software reference material provided
8 chip selects for external framers
8 interrupt inputs for external framers
Octet- and bit-level cell delineation
•
•
•
•
•
Applications
•
•
•
•
•
Cell Relay Service
ATM switch ports
DSLAM ports
SAM ports
ATM CPE ports
Functional Block Diagram
Host
RS8228
LCs[7]
LCs[0]
LInt~[7]
LInt~[0]
Interrupt
Status
Microprocessor Interface
UTOPIA
Level 2
Multi-PHY
Tx/Rx FIFO
4 Cells
ATM
Layer
Device
8/16
UTOPIA
Level 2
Interface
External
PMD
or
Framer
Framer
(Line)
Interface
External
PMD
or
Framer
Cell Processor
Line
Interface
Port 0
G.804 Cell Framer
Cell Processor
Line
Interface
Port 7
G.804 Cell Framer
Tx/Rx FIFO
4 Cells
Ordering Information
Model Number
RS8228EBG
Manufacturing
Part Number
28228-11
Product
Revision
A
Package
272-pin BGA
Operating Temperature
-40
°
C to 85
°
C
Copyright © 1998 Rockwell Semiconductor Systems, Inc. All rights reserved.
Print date: September 1998
Rockwell Semiconductor Systems, Inc. reserves the right to make changes to its products or specifications to improve
performance, reliability, or manufacturability. Information furnished is believed to be accurate and reliable. However, no
responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its
use. No license is granted by its implication or otherwise under any patent or intellectual property rights of Rockwell
Semiconductor Systems, Inc.
Rockwell Semiconductor Systems, Inc. products are not designed or intended for use in life support appliances, devices, or
systems where malfunction of a Rockwell Semiconductor Systems, Inc. product can reasonably be expected to result in personal
injury or death. Rockwell Semiconductor Systems, Inc. customers using or selling Rockwell Semiconductor Systems, Inc.
products for use in such applications do so at their own risk and agree to fully indemnify Rockwell Semiconductor Systems, Inc.
for any damages resulting from such improper use or sale.
®
Bt is a registered trademark of Rockwell Semiconductor Systems, Inc. SLC is a registered trademark of AT&T Technologies,
Inc. Product names or services listed in this publication are for identification purposes only, and may be trademarks or registered
trademarks of their respective companies. All other marks mentioned herein are the property of their respective holders.
Specifications are subject to change without notice.
PRINTED IN THE UNITED STATES OF AMERICA
RS8228 Features
Framer (Line) Interface Section
•
•
Programmable bit or byte synchronous serial interface
Direct connection to external Rockwell components for:
– T1/E1
– DS3
– E3
– J2
– xDSL
– General purpose mode
Interrupt and chip select signals for each external framer
Control and Status
Microprocessor interface
•
•
•
•
•
•
•
•
Asynchronous SRAM-like interface mode
Synchronous, glueless Bt8233/RS8234 SAR interface mode
8-bit data bus
Open-drain interrupt output
Open-drain ready output
8 - 50 MHz operation
All control registers are read/write
Four programmable status indicator signals per port
•
Cell Alignment Framing Section
•
Supports ATM cell interface for:
– Circuit-based physical layer
– Cell-based physical layer
Passes or rejects idle cells or selected cells based on header
register configuration
Recovers cell alignment from HEC
Performs single-bit HEC header error correction and single-
or multiple-bit detection
Generates cell status bits, cell counts, and error counts
Inserts headers and generates HEC
Inserts idle cells when no traffic is ready
Counters/status register section
•
•
•
•
•
Summary interrupt indications
Configuration of interrupt enables
One-second status latching
One-second counter latching
Counters for:
– LOCD events
– Corrected HEC errors
– Uncorrected HEC errors
– Transmitted cells
– Matching received cells
– Non-matching received cells
•
•
•
•
•
•
UTOPIA Level 2 Interface
•
•
•
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PHY cell to UTOPIA interface
50 MHz maximum clock rate
8/16-bit data path interface
Multi-PHY capability
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