NOT RECOMMENDED FOR NEW DESIGNS
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FN7875
Rev. 1.00
February 27, 2014
TW2809C
Multichannel H.264 Audio/Video Codec
Features
TW2809C is a high performance and cost
effective multi-channel H.264 codec solution
designed for security surveillance market. It is
capable of encoding and decoding maximum 8
channels standard definition (SD) video in real
time. It can do high definition (HD) 1080x60i
encode or decode at real time too. Each video
channel can be independently controlled in terms
of encode / decode mode, frame rate, bit rate,
and resolution. TW2809C is an ideal H.264 codec
candidate for different DVR platforms such as
16CH SD or 16CH CIF.
Peripheral I/F
External 16-bit DDR2 SDRAM @ 400MHz
32-bit PCI target for host communications @
33/66MHz
Operating Voltage
1.2V for core
3.3V for I/O pad
1.8V for DDR2 DRAM I/O
Physical
PBGA-320, 27mmx27mm, 1.27mm lead pitch
1.2W power consumption
Video Features
Real time full-duplex video codec compliant to
H.264 main profile standard
Supports real time full duplex 9 channel SD
encode and/or decode
Supports CIF JPEG or H.264 network stream
encode
Supports CBR and VBR
Four video input ports compliant to BT.656 up
to 108MHz
Four video output ports compliant to BT.656 up
to 108MHz
Two video input ports compliant to BT.1120 at
74.25MHz
Two video output ports compliant to BT.1120 at
74.25MHz
Audio Features
Real time 16 channel encode and 1 channel
decode compliant to ADPCM standard.
Independent digital audio input and output I/F
compliant to
I
2
S
standard
Audio sample rate from 8kHz to 48kHz
FN7875 Rev. 1.00
February 27, 2014
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TW2809C
Table of Contents
TW2809 Register Definition Overview ................................................................................................................... 18
TW2809 Memory Map .............................................................................................................................................. 18
Interrupt Scheme....................................................................................................................................................... 19
Interrupt register............................................................................................................................................... 19
Interrupt protocol.............................................................................................................................................. 19
PCI Register Definitions ................................................................................................................................................. 20
PCI Register 00 .......................................................................................................................................................... 21
PCI Register 04 .......................................................................................................................................................... 21
PCI Register 08 .......................................................................................................................................................... 22
PCI Register 0c .......................................................................................................................................................... 22
PCI Register 10-24 .................................................................................................................................................... 23
PCI Register 28 .......................................................................................................................................................... 23
PCI Register 2c .......................................................................................................................................................... 24
PCI Register 30 .......................................................................................................................................................... 24
PCI Register 34 .......................................................................................................................................................... 25
PCI Register 38 .......................................................................................................................................................... 25
PCI Register 3c .......................................................................................................................................................... 26
Pin Mux Register Definitions ......................................................................................................................................... 27
UART Pin Mux Configuration .................................................................................................................................... 27
Descriptions....................................................................................................................................................... 27
GPIO[7:0] Pin Mux Configuration ........................................................................................................................... 28
Descriptions....................................................................................................................................................... 28
GPIO[15:8] Pin Mux Configuration......................................................................................................................... 29
Descriptions....................................................................................................................................................... 29
GPIO[23:16] Pin Mux Configuration ...................................................................................................................... 30
Descriptions....................................................................................................................................................... 30
GPIO[31:24] Pin Mux Configuration ...................................................................................................................... 31
GPIO[39:32] pin mux configuration ...................................................................................................................... 32
Descriptions....................................................................................................................................................... 32
GPIO[47:40] Pin Mux Configuration ...................................................................................................................... 33
Descriptions....................................................................................................................................................... 33
GPIO[55:48] pin mux configuration ...................................................................................................................... 34
Descriptions....................................................................................................................................................... 34
PDMA Register Definitions ............................................................................................................................................ 35
Master Mode .............................................................................................................................................................. 35
PDMA Interrupt Status Register for FW ........................................................................................................ 35
Descriptions....................................................................................................................................................... 36
PDMA Master TX and RX Interrupt Status Register (optional) .................................................................. 36
Descriptions....................................................................................................................................................... 36
PDMA Master TX and RX Endian Control Register ...................................................................................... 37
Descriptions....................................................................................................................................................... 37
PDMA Master TX Control Register ................................................................................................................. 38
Descriptions....................................................................................................................................................... 38
PDMA Master TX Buffer ID Register .............................................................................................................. 38
Descriptions....................................................................................................................................................... 38
PDMA Master TX Target Start Address Register ......................................................................................... 39
Descriptions....................................................................................................................................................... 39
PDMA Master TX Total Length Register ........................................................................................................ 39
PDMA Master TX 2D XY Start Register ......................................................................................................... 39
PDMA Master RX Control Register ................................................................................................................ 40
Descriptions....................................................................................................................................................... 40
PDMA Master RX Buffer ID Register ............................................................................................................. 40
Descriptions....................................................................................................................................................... 40
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February 27, 2014
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TW2809C
PDMA Master RX Source Start Address Register ........................................................................................ 41
Descriptions....................................................................................................................................................... 41
PDMA Master RX Total Length Register ....................................................................................................... 41
PDMA Master RX 2D XY Start Register......................................................................................................... 41
Slave Mode ................................................................................................................................................................. 42
PDMA Slave TX Control Register .................................................................................................................... 42
Descriptions....................................................................................................................................................... 42
PDMA Slave TX Buffer ID Register ................................................................................................................. 43
Descriptions....................................................................................................................................................... 43
PDMA Slave TX Total Length Register .......................................................................................................... 43
Descriptions....................................................................................................................................................... 43
PDMA Slave TX 2D XY Start Register ............................................................................................................ 44
PDMA Slave RX Control Register ................................................................................................................... 44
Descriptions....................................................................................................................................................... 44
PDMA Slave RX Buffer ID Register ................................................................................................................ 45
Descriptions....................................................................................................................................................... 45
PDMA Slave RX Total Length Register .......................................................................................................... 45
Descriptions....................................................................................................................................................... 45
PDMA Slave RX 2D XY Start Register ........................................................................................................... 45
PDMA Slave Interrupt Status Register .......................................................................................................... 46
Descriptions....................................................................................................................................................... 46
Communication Between FW and Host ................................................................................................................. 47
The Communication Command Register from Host Driver ....................................................................... 47
Descriptions....................................................................................................................................................... 47
The first Extra Communication Register from Host Driver ........................................................................ 47
Descriptions....................................................................................................................................................... 47
The Second Extra Communication Register from Host Driver .................................................................. 48
The Communication Command Register from FW ..................................................................................... 48
Descriptions....................................................................................................................................................... 48
The First Extra Communication Register from FW...................................................................................... 49
Descriptions....................................................................................................................................................... 49
The Second Extra Communication Register from FW ................................................................................ 49
Descriptions....................................................................................................................................................... 49
Interrupt Status for PCI Host Driver ........................................................................................................................ 50
PDMA Interrupt Status Register for PCI channel ........................................................................................ 50
Descriptions....................................................................................................................................................... 51
Global Control Register Definitions .............................................................................................................................. 51
Normal Interrupt ........................................................................................................................................................ 51
Descriptions....................................................................................................................................................... 51
Codec Video Channel ................................................................................................................................................ 52
Descriptions....................................................................................................................................................... 52
Software Reset .......................................................................................................................................................... 53
Description ........................................................................................................................................................ 54
Timer Period Register ............................................................................................................................................... 55
Descriptions....................................................................................................................................................... 55
Encode Mode Register .............................................................................................................................................. 55
Fast Interrupt.............................................................................................................................................................. 56
Descriptions....................................................................................................................................................... 56
Encoder Parameter Register 0 ................................................................................................................................ 57
Encoding Parameter Register 1 .............................................................................................................................. 57
Encoder Parameter Register 2 ................................................................................................................................ 58
Encoder Parameter Register 3 ................................................................................................................................ 58
Timer 0 Count ............................................................................................................................................................ 59
Timer 1 Count ............................................................................................................................................................ 59
Timer 2 Count ............................................................................................................................................................ 59
Timer 3 Count ............................................................................................................................................................ 59
FN7875 Rev. 1.00
February 27, 2014
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TW2809C
Encoder Parameter Register 4 ................................................................................................................................ 60
Encoder Parameter Register 5 ................................................................................................................................ 60
Encoder Parameter Register 6 ................................................................................................................................ 61
Encoder Parameter Register 7 ................................................................................................................................ 61
Encoder Parameter Register 8 ................................................................................................................................ 61
Encoder Parameter Register 9 ................................................................................................................................ 62
Encoder Parameter Register 10 ............................................................................................................................. 62
Encoder Parameter Register 11 ............................................................................................................................. 63
Encoder Parameter Register 12 ............................................................................................................................. 63
Watch Dog Limit ........................................................................................................................................................ 63
Timer Control Register .............................................................................................................................................. 64
Descriptions....................................................................................................................................................... 64
Timer 1 Control Register .......................................................................................................................................... 65
Timer 2 Control Register .......................................................................................................................................... 65
Timer 3 Control Register .......................................................................................................................................... 66
Host Interface Register Definitions .............................................................................................................................. 67
HIF Interrupt ............................................................................................................................................................... 67
Descriptions....................................................................................................................................................... 67
Device ID 68
PCI Class Code ........................................................................................................................................................... 68
PCI Sub-system ID ..................................................................................................................................................... 69
PCI Header Info .......................................................................................................................................................... 69
DDR Mode Register ................................................................................................................................................... 70
DDR Timing Control Register 0 ............................................................................................................................... 72
Descriptions....................................................................................................................................................... 72
DDR Timing Control Register 1 ............................................................................................................................... 72
Descriptions....................................................................................................................................................... 72
FW PDMA Control Register ...................................................................................................................................... 73
FW PDMA Command Register ................................................................................................................................ 73
I2C Register Definitions.................................................................................................................................................. 74
I2C Interrupt Register ............................................................................................................................................... 74
Descriptions....................................................................................................................................................... 74
I2C Mode Select Register ......................................................................................................................................... 75
Descriptions....................................................................................................................................................... 75
I2C Write Register0, Register1, Register2, Register3 ......................................................................................... 75
Descriptions....................................................................................................................................................... 75
I2C Write Register4, Register5, Register6, Register7 ......................................................................................... 76
Descriptions....................................................................................................................................................... 76
I2C Write Register8, Register9, Register10, Register11 .................................................................................... 76
Descriptions....................................................................................................................................................... 76
I2C Write Register12, Register13, Register14, Register15 ............................................................................... 77
Descriptions....................................................................................................................................................... 77
I2C Write Register16, Register17, Register18, Register19 ............................................................................... 77
Descriptions....................................................................................................................................................... 77
I2C Write Register20, Register21, Register22, Register23 ............................................................................... 78
Descriptions....................................................................................................................................................... 78
I2C Write Register24, Register25, Register26, Register27 ............................................................................... 78
Descriptions....................................................................................................................................................... 78
I2C Write Register28, Register29, Register30, Register31 ............................................................................... 79
Descriptions....................................................................................................................................................... 79
I2C Read Register0, Register1, Register2, Register3 ......................................................................................... 79
Descriptions....................................................................................................................................................... 79
I2C Read Register4, Register5, Register6, Register7 ......................................................................................... 80
Descriptions....................................................................................................................................................... 80
I2C Read Register8, Register9, Register10, Register11 .................................................................................... 80
Descriptions....................................................................................................................................................... 80
FN7875 Rev. 1.00
February 27, 2014
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TW2809C
I2C Read Register12, Register13, Register14, Register15 ............................................................................... 81
Descriptions....................................................................................................................................................... 81
I2C Read Register16, Register17, Register18, Register19 ............................................................................... 81
Descriptions....................................................................................................................................................... 81
I2C Read Register20,Register21,Register22,Register23 .................................................................................. 82
Descriptions....................................................................................................................................................... 82
I2C Read Register24,Register25,Register26,Register27 .................................................................................. 82
Descriptions....................................................................................................................................................... 82
I2C Read Register28, Register29, Register30, Register31 ............................................................................... 83
Descriptions....................................................................................................................................................... 83
I2C Master Mode Protocol ....................................................................................................................................... 84
Write CBUS 32 bit registers: ........................................................................................................................... 84
Read CBUS 32 bit registers: ........................................................................................................................... 84
UART Register Definitions .............................................................................................................................................. 86
UART Interrupt Enable Register .............................................................................................................................. 86
Descriptions....................................................................................................................................................... 86
UART Interrupt Status Register ............................................................................................................................... 86
Descriptions....................................................................................................................................................... 86
UART Line Control Register(LCR) ............................................................................................................................ 87
Descriptions....................................................................................................................................................... 87
UART Divisor Latch Byte 1 Register(LSB) .............................................................................................................. 88
Descriptions....................................................................................................................................................... 88
UART Divisor Latch Byte 2 Register (MSB) ............................................................................................................ 89
Descriptions....................................................................................................................................................... 89
UART Internal Interrupt Enable Register(IER) ....................................................................................................... 90
Descriptions....................................................................................................................................................... 90
UART Interrupt Identification Register(IIR) ........................................................................................................... 91
Descriptions....................................................................................................................................................... 91
UART FIFO Control Register(FCR)............................................................................................................................ 92
Descriptions....................................................................................................................................................... 92
UART Modem Control Register(MCR) ..................................................................................................................... 93
Descriptions....................................................................................................................................................... 93
UART Line Status Register(LSR) ............................................................................................................................. 94
Descriptions....................................................................................................................................................... 95
UART Modem Status Register(MSR) ...................................................................................................................... 96
Descriptions....................................................................................................................................................... 96
UART Receiver Buffer................................................................................................................................................ 97
Descriptions....................................................................................................................................................... 97
UART Transmitter Holding Register ........................................................................................................................ 97
Descriptions....................................................................................................................................................... 97
GPIO Register Definitions............................................................................................................................................... 98
GPIO Interrupt Enable Register ............................................................................................................................... 98
Descriptions....................................................................................................................................................... 98
GPIO Interrupt Status Register ................................................................................................................................ 99
Descriptions....................................................................................................................................................... 99
GPIO Line Driving Register0 .................................................................................................................................... 99
Descriptions....................................................................................................................................................... 99
GPIO Line Driving Register1 ................................................................................................................................. 100
Descriptions.................................................................................................................................................... 100
GPIO Line Control Register0 ................................................................................................................................. 100
Descriptions.................................................................................................................................................... 100
GPIO Line Control Register1 ................................................................................................................................. 101
Descriptions.................................................................................................................................................... 101
GPIO Line Load Register0 ..................................................................................................................................... 101
Descriptions.................................................................................................................................................... 101
GPIO Line Load Register1 ..................................................................................................................................... 102
FN7875 Rev. 1.00
February 27, 2014
Page 5 of 130
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