TM
82C83H
CMOS Octal Latching Inverting Bus Driver
Description
The Intersil 82C83H is a high performance CMOS Octal
Latching Buffer manufactured using a self-aligned silicon gate
CMOS process (Scaled SAJI IV). The 82C83H provides an 8-
bit parallel latch/buffer in a 20 lead pin package. The active
high strobe (STB) input allows transparent transfer of data
and latches data on the negative transition of this signal. The
active low output enable (OE) permits simple interface to
microprocessor systems. The 82C83H provides inverted data
at the outputs.
March 1997
Features
• Full 8-Bit Parallel Latching Buffer
• Bipolar 8283 Compatible
• Three-State Inverting Outputs
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . . 25ns Max
• Gated Inputs
- Reduce Operating Power
- Eliminate the Need for Pull-Up Resistors
• Single 5V Power Supply
• Low Power Operation
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
• Operating Temperature Ranges
- C82C83H . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to +70
o
C
- I82C83H . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
- M82C83H . . . . . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Ordering Information
PART NO.
CP82C83H
IP82C83H
CS82C83H
IS82C83H
CD82C83H
ID82C83H
MD82C83H/B
8406702RA
MR82C83H/B
84067022A
SMD#
20 Pad CLCC
SMD#
20 Ld CERDIP
20 Ld PLCC
PACKAGE
20 Ld PDIP
TEMP RANGE
0
o
C to +70
o
C
-40
o
C to +85
o
C
0
o
C to +70
o
C
-40
o
C to +85
o
C
0
o
C to +70
o
C
-40
o
C to +85
o
C
0
o
C to +70
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
PKG. NO
E20.3
E20.3
N20.35
N20.35
F20.3
F20.3
F20.3
F20.3
J20.A
J20.A
Pinouts
82C83H (PDIP, CERDIP)
TOP VIEW
DI
0
DI
1
DI
2
DI
3
DI
4
DI
5
DI
6
DI
7
OE
1
2
3
4
5
6
7
8
9
20 V
CC
19 DO
0
18 DO
1
17 DO
2
16 DO
3
15 DO
4
14 DO
5
13 DO
6
12 DO
7
11 STB
9
OE
10
GND
11
STB
12
DO
7
13
DO
6
DI
3
DI
4
DI
5
DI
6
DI
7
4
5
6
7
8
18 DO
1
17 DO
2
16 DO
3
15 DO
4
14 DO
5
82C83H (PLCC, CLCC)
TOP VIEW
DO
0
19
V
CC
20
DI
2
DI
1
2
DI
0
1
3
GND 10
TRUTH TABLE
STB
X
H
H
↓
H = Logic One
L = Logic Zero
X = Don‘t Care
OE
H
L
L
L
DI
X
L
H
X
DO
HI-Z
H
L
†
PIN
DI
0
- DI
7
DO
0
- DO
7
STB
OE
PIN NAMES
DESCRIPTION
Data Input Pins
Data Output Pins
Active High Strobe
Active Low Output Enable
HI-Z = High Impedance
↓
= Negative Transition
†
= Latched to Value of Last
Data
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
FN2971.1
281
82C83H
Functional Diagram
DI0
D Q
CLK
DO0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DO1
DO2
DO3
DO4
DO5
DO6
DO7
state). The 82C8X series gated inputs mean that this condi-
tion will occur only during the time the device is in the trans-
parent mode (STB = logic one). ICC remains below the
maximum ICC standby specification of 10µA during the time
inputs are disabled, thereby greatly reducing the average
power dissipation of the 82C8X series devices.
V
CC
P
OE
DATA IN
V
CC
P
N
P
INTERNAL
DATA
N
STB
OE
N
FIGURE 2. 82C86H/87H GATED INPUTS
Gated Inputs
During normal system operation of a latch, signals on the
bus at the device inputs will become high impedance or
make transitions unrelated to the operation of the latch.
These unrelated input transitions switch the input circuitry
and typically cause an increase in power dissipation in
CMOS devices by creating a low resistance path between
V
CC
and GND when the signal is at or near the input switch-
ing threshold. Additionally, if the driving signal becomes high
impedance (``float'' condition), it could create an indetermi-
nate logic state at the inputs and cause a disruption in
device operation.
The Intersil 82C8X series of bus drivers eliminates these
conditions by turning off data inputs when data is latched
(STB = logic zero for the 82C82/83H) and when the device is
disabled (OE = logic one for the 82C86H/87H). These gated
inputs disconnect the input circuitry from the V
CC
and
ground power supply pins by turning off the upper P-channel
and lower N-channel (See Figures 1 and 2). No current flow
from V
CC
to GND occurs during input transitions and invalid
logic states from floating inputs are not transmitted. The next
stage is held to a valid logic level internal to the device.
V
CC
P
P
STB
DATA IN
N
N
P
INTERNAL
DATA
V
CC
Decoupling Capacitors
The transient current required to charge and discharge the
300pF load capacitance specified in the 82C83H data sheet
is determined by
I = C
L
(dv/dt)
Assuming that all outputs change state at the same time and
that dv/dt is constant;
(
V
CC
×
80 percent
)
I
=
C
L
--------------------------------------------------------
t
⁄
t
R
F
(EQ. 1)
where t
R
= 20ns, V
CC
= 5.0V, C
L
= 300pF on each eight out-
puts.
I = (8 x 300 x 10
-12
) x (5.0V x 0.8)/(20 x 10
-9
) = 480mA
This current spike may cause a large negative voltage spike on
V
CC
which could cause improper operation of the device. To fil-
ter out this noise, it is recommended that a 0.1µF ceramic disc
capacitor be placed between V
CC
and GND at each device,
with placement being as near to the device as possible.
ALE
MULTI-
PLEXED
BUS
ICC
ADDRESS
ADDRESS
V
CC
P
V
CC
P
STB
N
P
INTERNAL
DATA
N
N
N
DATA IN
FIGURE 1. 82C82/83H
D.C. input voltage levels can also cause an increase in ICC
if these input levels approach the minimum V
IH
or maximum
V
IL
conditions. This is due to the operation of the input cir-
cuitry in its linear operating region (partially conducting
FIGURE 3. SYSTEM EFFECTS OF GATED INPUTS
282
82C83H
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage . . . . . . . . . . . . GND 0.5V to V
CC
+0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical)
θ
JAo
C/W
θ
JCo
C/W
CERDIP Package . . . . . . . . . . . . . . . .
70
16
CLCC Package . . . . . . . . . . . . . . . . . .
80
20
PDIP Package . . . . . . . . . . . . . . . . . . .
75
N/A
PLCC Package . . . . . . . . . . . . . . . . . .
75
N/A
Storage Temperature Range . . . . . . . . . . . . . . . . .-65
o
C to +150
o
C
Max Junction Temperature Ceramic Package. . . . . . . . . . . . . . +175
o
C
Max Junction Temperature Plastic Package . . . . . . . . . . . . . . . +150
o
C
Lead Temperature (Soldering 10s) (PLCC - Lead Tips Only). . +300
o
C
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
C82C83H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0
o
C to +70
o
C
I82C83H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
M82C83H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
V
CC
= 5.0V
±
10%; T
A
= 0
o
C to +70
o
C (C82C83H);
T
A
= -40
o
C to +85
o
C (I82C83H);
T
A
= -55
o
C to +125
o
C (M82C83H)
SYMBOL
V
IH
V
IL
V
OH
V
OL
I
I
I
O
lCCSB
PARAMETER
Logical One Input Voltage
MIN
2.0
2.2
MAX
-
UNITS
V
TEST CONDITIONS
C82C83H, I82C83H,
M82C83H, (Note 1)
Logical Zero Input Voltage
Logical One Output Voltage
3.0
V
CC
-0.4V
0.8
-
V
V
I
OH
= -8mA,
I
OH
= -100mA, OE = GND
I
OL
= 20mA, OE = GND
V
IN
= GND or V
CC
,
DIP Pins 1-9,11
V
O
= GND or OE
≥
V
CC
-0.5V
DIP Pins 12-19
V
IN
= V
CC
or GND
V
CC
= 5.5V Outputs Open
T
A
= +25
o
C, V
CC
= 5V, Typical
(See Note 2)
Logical Zero Output Voltage
Input Leakage Current
-10
0.45
10
V
µA
µA
µA
Output Leakage Current
-10
10
Standby Power Supply Current
-
10
IC COP
Operating Power Supply Current
-
1
mA/
MHz
NOTES:
1. V
IH
is measured by applying a pulse of magnitude = V
lHMIN
to one data Input at a time and checking the corresponding device output for
a valid logical 1 - during valid input high time. Control pins (STB, CE) are tested separately with all device data input pins at V
CC
-0.4V.
2. Typical ICCOP = 1 mA/MHz of STB cycle time. (Example: 5MHz
µP,
ALE = 1.25MHz, ICCOP = 1.25mA).
Capacitance
T
A
= +25
o
C
SYMBOL
C
IN
C
OUT
PARAMETER
Input Capacitance
Output Capacitance
TYPICAL
13
20
UNITS
pF
pF
TEST CONDITIONS
FREQ = 1MHz, all measure-
ments are referenced to device
GND
283
82C83H
AC Electrical Specifications
V
CC
= 5.0V
±10%;
C
L
= 300pF (Note 1), FREQ = 1MHz
T
A
= 0
o
C to +70
o
C (C82C83H);
T
A
= -40
o
C to +85
o
C (l82C83H);
T
A
= -55
o
C to +125
o
C (M82C83H)
LIMITS
SYMBOL
(1) TlVOV
(2) TSHOV
(3) TEHOZ
(4) TELOV
(5) TlVSL
(6) TSLIX
(7) TSHSL
(8) TR, TF
NOTES:
1. Output load capacitance is rated 300pF for both ceramic and plastic packages.
2. All AC Parameters tested as per test load circuits. Input rise and tall times are driven at 1ns/V.
3. Input test signals must switch between V
IL
-0.4V and V
lH
+0.4V.
PARAMETER
Propagation Delay Input to Output
Propagation Delay STB to Output
Output Disable Time
Output Enable Time
Input to STB Set Up Time
Input to STB Hold Time
STB High Time
Input Rise/Fall Times
MIN
5
10
5
10
0
30
15
-
MAX
25
50
22
45
-
-
-
20
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
TEST CONDITIONS
See Notes 2, 3
See Notes 2, 3
See Notes 2, 3
See Notes 2, 3
See Notes 2, 3
See Notes 2, 3
See Notes 2, 3
See Notes 2, 3
Timing Waveforms
TR, TF (8)
INPUTS
2.0V
0.8V
TIVSL (5)
STB
TSHSL (7)
TSLIX
(6)
OE
TIVOV
(1)
OUTPUTS
VOL +0.1V
TSHOV (2)
TEHOZ (3)
VOH -0.1V
TELOV (4)
3.0V
0.45V
All Timing measurements are made at 1.5V unless otherwise noted.
FIGURE 4. TIMING WAVEFORMS
284
82C83H
Test Load Circuits
2.27V
91Ω
OUTPUT
TEST
POINT
300pF
(SEE NOTE)
OUTPUT
1.5V
180Ω
TEST
POINT
300pF
(SEE NOTE)
FIGURE 5. TIVOV, TSHOV
1.5V
51Ω
OUTPUT
TEST
POINT
300pF
(SEE NOTE)
FIGURE 6. TELOV OUTPUT HIGH ENABLE
2.27V
91Ω
OUTPUT
TEST
POINT
50pF
(SEE NOTE)
NOTE: Includes jig and stray capacitance.
FIGURE 7. TELOV OUTPUT LOW ENABLE
FIGURE 8. TEHOZ OUTPUT LOW/HIGH DISABLE
Burn-In Circuits
V
CC
V
CC
R4
20 19
18
17
16
15
14
9
10 11 12 13
R4
R4
R4
R4
R4
V
CC
2
R4
V
CC
2
R4
C1
F2
F2
R4
R4
R1
F2
F2
F2
F2
F2
F2
F2
F2
F0
R1
R1
R1
R1
R1
R1
R1
R1
9
10
12
11
R1
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
C1
A
A
A
A
A
A
A
A
F1
A
R2
V
CC
R2
F2
F2
F2
F2
F2
R4
R4
R4
R4
R4
4
5
6
7
8
3
2
R3
F0
FIGURE 9. MD82C83H CERDIP
FIGURE 10. MR82C83H CLCC
285
F1
R3
R4
V
CC
1
F2
2
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