Preliminary Data Sheet
144-pin SDRAM SODIMMs
64MB, 128MB, 256MB, 512MB
Features
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•
•
•
•
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JEDEC Standard 144-pin PC133 SDRAM SODIMM
Fast 5.4 ns Clock Access Time
Supports CAS Latency = 2, 3
On-board Serial Presence Detect (SPD)
Unbuffered 144-pin SODIMM
4K Refresh / 64ms (8K Refresh for 512MB DIMM)
Single 3.3V
±
0.3V Power Supply
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Symbol
Vss
Vss
DQ0
DQ32
DQ1
DQ33
DQ2
DQ34
DQ3
DQ35
Vdd
Vdd
DQ4
DQ36
DQ5
DQ37
DQ6
DQ38
DQ7
DQ39
Vss
Vss
DQMB0
DQMB4
DQMB1
DQMB5
Vdd
Vdd
A0
A3
A1
A4
A2
A5
Vss
Vss
Pin
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Symbol
DQ8
DQ40
DQ9
DQ41
DQ10
DQ42
DQ11
DQ43
Vdd
Vdd
DQ12
DQ44
DQ13
DQ45
DQ14
DQ46
DQ15
DQ47
Vss
Vss
NC
RSVD
NC
RSVD
CK0
CKE0
Vdd
Vdd
RAS#
CAS#
WE#
CKE1
S0#
A12
S1#
NC
Pin
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
Symbol
RSVD
CK1
Vss
Vss
RSVD
RSVD
RSVD
RSVD
Vdd
Vdd
DQ16
DQ48
DQ17
DQ49
DQ18
DQ50
DQ19
DQ51
Vss
Vss
DQ20
DQ52
DQ21
DQ53
DQ22
DQ54
DQ23
DQ55
Vdd
Vdd
A6
A7
A8
BA0
Vss
Vss
Pin
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
Symbol
Vss
A9
A10/AP
NC
Vdd
Vdd
DQMB2
DQMB6
DQMB3
DQMB7
Vss
Vss
DQ24
DQ56
DQ25
DQ57
DQ26
DQ58
DQ27
DQ59
Vdd
Vdd
DQ28
DQ60
DQ29
DQ61
DQ30
DQ62
DQ31
DQ63
Vss
Vss
SDA
SCL
Vdd
Vdd
Description
The Enhanced Memory Systems 64MB, 128MB, 256MB,
and 512MB Small Outline DIMMs (1.05-inch height) are the
fastest SODIMMs available for notebook and embedded
system applications. This PC133 product provides the lowest
cost for both PC133 and PC100 sockets. The fast 5.4 ns
clock access time allows unbuffered operation at 133 MHz
for lower memory latency, and lower costs than registered
DIMMs.
The 64MB module is organized as 8Mx64, the 128MB
module is organized as 16Mx64, the 256MB module is
organized as 32Mx64, and the 512MB module is organized
as 64Mx64. Each module has a serial presence EEPROM,
which contains information on the module type, module
organization, component speed, and other attributes relevant
to the system controller.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095;
http://www.edram.com
2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 1 of 15
Revision 1.0
144-pin SDRAM SODIMMs
64MB, 128MB, 256MB, 512MB
Pin Descriptions
Symbol
CK(0:1)
CKE(0:1)
S(0:1)#
RAS#, CAS#,
WE#
BA(0:1)
A(0:12)
Preliminary Data Sheet
Type
Input
Input
Input
Input
Input
Input
Function
Clocks: All SDRAM input signals are sampled on the positive edge of CK.
Clock Enables: CKE activate (high) or deactivate (low) the CK signals. Deactivating the clock initiates the
Power-Down and Self-Refresh operations (all banks idle), or Clock Suspend operation. CKE is synchronous until
the device enters Power-Down and Self-Refresh modes where it is asynchronous until the mode is exited.
Chip Select: S# enables (low) or disables (high) the command decoder. When the command decoder is
disabled, new commands are ignored but previous operations continue.
Command Inputs: Sampled on the rising edge of CK, these inputs define the command to be executed.
Bank Addresses: These inputs define to which of the 4 banks a given command is being applied.
Address Inputs: A0-A12 define the row address during the Bank Activate command. A0-A9 define the column
address during Read and Write commands. A10/AP invokes the Auto-precharge operation. During manual
Precharge commands, A10/AP low specifies a single bank precharge while A10/AP high precharges all banks.
The address inputs are also used to program the Mode Register.
Data I/O: Data bus inputs and outputs. For Write cycles, input data is applied to these pins and must be set-up
and held relative to the rising edge of clock. For Read cycles, the device drives output data on these pins after
the CAS latency is satisfied.
Data I/O Mask Inputs: DQMB0-7 inputs mask write data (zero latency) and acts as a synchronous output enable
(2-cycle latency) for read data.
Power Supply: +3.3 V
Ground
Serial Presence-Detect Data: SDA is a bi-directional pin used to transfer addresses and data into
and data out of the presence-detect portion of the module.
DQ(0:63)
DQMB(0-7)
V
DD
V
SS
SDA
Input/
Output
Input
Supply
Supply
Input/
Output
Input
-
-
-
SCL
RFU
DNU
NC
Serial Clock for Presence-Detect: SCL is used to synchronize the presence detect data transfer to
and from the module
Reserved for Future Use: These pins should be left unconnected.
Do not use.
No connect - open pin.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095;
http://www.edram.com
Page 2 of 15
2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.0
Preliminary Data Sheet
144-pin SDRAM SODIMMs
64MB, 128MB, 256MB, 512MB
64MB DIMM Functional Block Diagram – SM6408SDT
Clock Wiring
S0#
CK0
CK1
DQMB0
DQ(7:0)
DQMB4
U0
DQ(39:32)
10
2 SDRAMs
CK0, CK1
2 SDRAMs
10
DQMB1
DQ(15:8)
DQMB5
U1
DQ(47:40)
U5
U4
4 SDRAM
4 SDRAM
SCL
Serial PD
DQMB2
U2
DQ(23:16)
DQ(55:48)
DQMB6
U6
A0
A1
A2
SDA
DQMB3
U3
DQ(31:24)
DQMB7
U7
DQ(63:56)
BA0
BA1
A0-A11
Vdd
Vss
BA0 SDRAM U0-7
BA1 SDRAM U0-7
A0-A11 SDRAM U0-7
Vdd SDRAM U0-7
Vss SDRAM U0-7
RAS#
CAS#
WE#
CKE0
RAS# SDRAM U0-7
CAS# SDRAM U0-7
WE# SDRAM U0-7
CKE SDRAM U0-7
Note:
All DQ resistor values are 10 ohms.
All CK resistor values are 10 ohms.
U0-U7 are 8Mx8 PC133 SDRAM devices.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095;
http://www.edram.com
2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 3 of 15
Revision 1.0
144-pin SDRAM SODIMMs
64MB, 128MB, 256MB, 512MB
128MB DIMM Functional Block Diagram – SM12808ASDT
Preliminary Data Sheet
Clock Wiring
S0#
CK0
CK1
DQMB0
DQ(7:0)
DQMB4
U0
DQ(39:32)
10
2 SDRAMs
CK0, CK1
2 SDRAMs
10
DQMB1
DQ(15:8)
DQMB5
U1
DQ(47:40)
U5
U4
4 SDRAM
4 SDRAM
SCL
Serial PD
DQMB2
U2
DQ(23:16)
DQ(55:48)
DQMB6
U6
A0
A1
A2
SDA
DQMB3
U3
DQ(31:24)
DQMB7
U7
DQ(63:56)
BA0
BA1
A0-A11
Vdd
Vss
BA0 SDRAM U0-7
BA1 SDRAM U0-7
A0-A11 SDRAM U0-7
Vdd SDRAM U0-7
Vss SDRAM U0-7
RAS#
CAS#
WE#
CKE0
RAS# SDRAM U0-7
CAS# SDRAM U0-7
WE# SDRAM U0-7
CKE SDRAM U0-7
Note:
All DQ resistor values are 10 ohms.
All CK resistor values are 10 ohms.
U0-U7 are 16Mx8 PC133 SDRAM devices.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095;
http://www.edram.com
Page 4 of 15
2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.0
Preliminary Data Sheet
144-pin SDRAM SODIMMs
64MB, 128MB, 256MB, 512MB
256MB DIMM Functional Block Diagram – SM25608ASDT
Clock Wiring
S0#
S1#
DQMB0
10
DQMB4
U0L
DQ(7:0)
U0U
DQ(39:32)
U4L
U4U
CK0
12pf
PLL
4 SDRAMs
4 SDRAMs
4 SDRAMs
DQMB1
CK1
DQMB5
U1L
DQ(15:8)
U1U
DQ(47:40)
SCL
Serial PD
DQMB2
U2L
DQ(23:16)
U2U
DQ(55:48)
BA0
BA1
DQMB3
U3L
DQ(31:24)
U3U
DQ(63:56)
Vdd
Vss
RAS#
CAS#
Note:
All DQ resistor values are 10 ohms.
All CK resistor values are 10 ohms.
U0-U7 are stacked 16Mx8 PC133 SDRAM devices.
WE#
CKE0
CKE1
Vdd SDRAM U0-7
Vss SDRAM U0-7
RAS# SDRAM U0-7
CAS# SDRAM U0-7
WE# SDRAM U0-7
CKE0 SDRAM U0-3
CKE0 SDRAM U4-7
DQMB7
U7L
U7U
A0-A11
A0-A11 SDRAM U0-7
BA0 SDRAM U0-7
BA1 SDRAM U0-7
DQMB6
U6L
U6U
A0
A1
A2
CK0
CK1
PLL
Terminated
4 SDRAMs
10
U5L
U5U
12pf
SDA
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095;
http://www.edram.com
2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 5 of 15
Revision 1.0
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