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THAT120

产品描述Quad Low-Noise PNP Transistor Array
文件大小41KB,共2页
制造商ETC
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THAT120概述

Quad Low-Noise PNP Transistor Array

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T H AT
Corporation
FEATURES
·
·
·
·
·
·
Four Matched PNP Transistors
Low noise — 0.75
nV
Hz
Quad Low-Noise
PNP Transistor Array
THAT120
APPLICATIONS
·
·
·
·
·
·
Microphone Preamplifiers
Tape Head Preamplifiers
Current Sources
Current Mirrors
Log/Antilog Amplifiers
Multipliers
High Speed — 325 MHz f
t
Excellent Matching - 500
mV
(typ)
Dielectrically Isolated
-25 V V
CEO
DESCRIPTION
THAT120 is a quad, large-geometry monolithic
PNP transistor array which combines low noise, high
speed and excellent parametric matching. The large
geometry typically results in 25
W
base spreading re-
sistance, producing 0.75
nV Hz
voltage noise. This
makes these parts an excellent choice for low-noise
amplifier input stages.
Fabricated on a Complementary Bipolar Dielec-
trically Isolated process, all four transistors are elec-
trically isolated from each other by a layer of oxide.
The resulting low collector-to-substrate capacitance
produces a typical f
t
of 325 MHz, for AC perfor-
mance similar to 2N3906-class devices. The dielec-
tric isolation also minimizes crosstalk and provides
complete DC isolation.
Substrate biasing is not required for normal oper-
ation, though the substrate should be grounded to
optimize speed. The one-chip construction assures
excellent parameter matching and tracking over tem-
perature.
7
8
9
10
4
11
12
13
SUB
14
NC
1
Q2 Q1
3
2
Q4 Q3
6
5
0.060
(1.52)
Typ.
1
0.750±0.004
(19.05±0.10)
0.25±.004
(6.35±0.10)
0.050
(1.27)
Typ
0.32 Max.
(8.13)
0.125±0.004
(3.18±0.10)
0.157 0.245
(3.99) (6.2)
Max Max
1
0.018 (0.46)
Max
0.10 Typ.
(2.54)
0.075
(1.91)
0.018
(0.46)
0.010
(0.25)
0.344 (8.74)
Max
0.069
(1.75)
Max
0.010
(0.25)
Max
Figure 1. Pin
Configuration
Figure 2. Dual-In-Line Package Outline
Figure 3. Surface Mount Package Outline
THAT Corporation; 45 Sumner St., Milford, Massachusetts; 01757-1656; USA
Tel: +1 (508) 478-9200; Fax: +1 (508) 478-0990; Web: www.thatcorp.com

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