THC63LVD104A Rev.1.0
THine
THC63LVD104A
90MHz 30Bits COLOR LVDS Receiver
General Description
The THC63LVD104A receiver is designed to support
pixel data transmission between Host and Flat Panel
Display from NTSC up to WXGA resolutions. The
THC63LVD104A converts the LVDS data streams back
into 35bits of CMOS/TTL data with rising edge or fall-
ing edge clock for convenient with a variety of LCD
panel controllers.At a transmit clock frequency of
90MHz, 30bits of RGB data and 5bits of timing and
control data (HSYNC,VSYNC,DE,CNTL1,CNTL2)
are transmitted at an effective rate of 630Mbps per
LVDS channel.Using a 90MHz clock, the data through-
put is 394Mbytes per second.
Features
•
Wide dot clock range: 8-90MHz suited for NTSC,
VGA, SVGA, XGA, and WXGA
•
•
•
•
•
•
•
PLL requires no external components
50% output clock duty cycle
TTL clock edge programmable
Power down mode
Low power single 3.3V CMOS design
64pin TQFP
Backward compatible with THC63LVDF64x
(18bits) / F84x(24bits)
Block Diagram
LVDS INPUT
RA+/-
SERIAL TO PARALLEL
RB+/-
RC+/-
RD+/-
RE+/-
RCLK+/-
(8 to90MHz)
CMOS/TTL OUTPUT
7
7
7
7
7
PLL
RA6-RA0
RB6-RB0
RC6-RC0
RD6-RD0
RE6-RE0
CLKOUT
CMOS/TTL INPUT
TEST
PD
OE
R/F
Copyright 2003 THine Electronics, Inc. All rights reserved
1
THine Electronics, Inc.
THC63LVD104A Rev.1.0
THine
Pin Out
RA-
RA+
RB-
RB+
LVCC
RC-
RC+
RCLK-
RCLK+
LGND
RD-
RD+
RE-
RE+
PGND
PVCC
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VCC
RA0
RA1
RA2
GND
RA3
RA4
RA5
RA6
RB0
RB1
VCC
RB2
RB3
RB4
RB5
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
RB6
CLKOUT
GND
RC0
RC1
RC2
RC3
RC4
RC5
VCC
RC6
RD0
RD1
RD2
RD3
RD4
Copyright 2003 THine Electronics, Inc. All rights reserved
GND
TEST
PD
OE
R/F
RE6
RE5
RE4
VCC
RE3
RE2
RE1
RE0
RD6
RD5
GND
2
THine Electronics, Inc.
THC63LVD104A Rev.1.0
THine
Pin Description
Pin Name
RA+, RA-
RB+, RB-
RC+, RC-
RD+, RD-
RE+,RE-
RCLK+, RCLK-
RA6 ~ RA0
RB6 ~ RB0
RC6 ~ RC0
RD6 ~ RD0
RE6 ~ RE0
TEST
PD
OE
R/F
VCC
CLKOUT
GND
LVCC
LGND
PVCC
PGND
Pin #
50, 49
52, 51
55, 54
60, 59
62, 61
57, 56
40,41,42,43,45,46,47
32,33,34,35,36,38,39
22,24,25,26,27,28,29
14,15,17,18,19,20,21
6,7,8,10,11,12,13
2
3
4
5
9,23,37,48
31
1,16,30,44
53
58
64
63
Type
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
Power
OUT
Ground
Power
Ground
Power
Ground
Test pin, must be “L” for normal operation.
H: Normal operation,
L: Power down (all outputs are “L”)
H:Output enable (Normal operation).
L:Output disable(all outputs are Hi-Z)
Output Clock Triggering Edge Select.
H: Rising edge, L: Falling edge
Power Supply Pins for TTL outputs and digital
circuitry.
Clock out.
Ground Pins for TTL outputs and digital cir-
cuitry.
Power Supply Pin for LVDS inputs.
Ground Pin for LVDS inputs.
Power Supply Pin for PLL circuitry.
Ground Pin for PLL circuitry.
CMOS/TTL Data Outputs.
LVDS Clock In.
LVDS Data In.
Description
PD
0
0
0
0
1
1
1
1
** Rxn
x = A,B,C,D,E
n = 0,1,2,3,4,5,6
R/F
0
0
1
1
0
0
1
1
OE
0
1
0
1
0
1
0
1
Data Outputs
(Rxn)
Hi-Z
All 0
Hi-Z
All 0
Hi-Z
Data Out
Hi-Z
Data Out
CLKOUT
Hi-Z
Fixed Low
Hi-Z
Fixed Low
Hi-Z
It latches output data on falling edge.
Hi-Z
It latches output data on rising edge.
Copyright 2003 THine Electronics, Inc. All rights reserved
3
THine Electronics, Inc.
THC63LVD104A Rev.1.0
THine
Absolute Maximum Ratings
1
Supply Voltage (V
CC
)
CMOS/TTL Input Voltage
CMOS/TTL Output Voltage
LVDS Receiver Input Voltage
Output Current
Junction Temperature
Storage Temperature Range
Resistance to soldering heat
Maximum Power Dissipation @+25
°C
-0.3V ~ +4.0V
-0.3V ~ (V
CC
+ 0.3V)
-0.3V ~ (V
CC
+ 0.3V)
-0.3V ~ (V
CC
+ 0.3V)
-30mA ~ 30mA
+125
°C
-55
°C
~ +125
°C
+260
°C
/10sec
1.0W
Electrical Characteristics
CMOS/TTL DC Specifications
V
CC
= 3.0V ~ 3.6V, Ta = 0
°C
~ +70
°C
Symbol
V
IH
V
IL
V
OH
Parameter
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
I
OH
= -4mA (data)
I
OH
= -8mA (clock)
I
OL
= 4mA (data)
I
OL
= 8mA (clock)
0V
≤
V
IN
≤
V
CC
Conditions
Min.
2.0
GND
2.4
Typ.
Max.
V
CC
0.8
Units
V
V
V
V
OL
I
INC
Low Level Output Voltage
Input Current
0.4
±
10
V
µA
LVDS Receiver DC Specifications
V
CC
= 3.0V ~ 3.6V, Ta = 0
°C
~ +70
°C
Symbol
V
TH
V
TL
I
INL
Parameter
Differential Input High Threshold
Differential Input Low Threshold
Input Current
Conditions
V
OC
= 1.2V
V
OC
= 1.2V
V
IN
= 2.4V / 0V
V
CC
= 3.6V
-100
±
20
Min.
Typ.
Max.
100
Units
mV
mV
µA
1. “Absolute Maximum Ratings” are those valued beyond which the safety of the device can not be guaranteed. They
are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics”
specify conditions for device operation.
Copyright 2003 THine Electronics, Inc. All rights reserved
4
THine Electronics, Inc.
THC63LVD104A Rev.1.0
THine
V
CC
= 3.0V ~ 3.6V, Ta = 0
°C
~ +70
°C
Supply Current
Symbol
I
RCCG
Parameter
Receiver Supply
Current
(Gray Scale Pattern)
Receiver Supply
I
RCCW
Current
(Checker Pattern)
I
RCCS
Receiver Power Down
Supply Current
PD = L
f
CLKOUT
= 90MHz
f
CLKOUT
= 90MHz
Conditions
CL=8pF,
Vcc=3.3V
CL=8pF,
Vcc=3.3V
Typ.
70
Max.
Units
mA
112
mA
10
µA
Copyright 2003 THine Electronics, Inc. All rights reserved
5
THine Electronics, Inc.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
