1.8 V CapSense Controller with
SmartSense™ Auto-tuning –
31 Buttons, 6 Sliders
1.8 V CapSense
®
Controller with SmartSense™ Auto-tuning Support
CY8C20x37/37S/47/47S/67/67S
®
Features
■
QuietZone™ Controller
❐
Patented Capacitive Sigma Delta PLUS (CSD PLUS™)
sensing algorithm for robust performance
❐
High Sensitivity (0.1 pF) and best-in-class SNR performance
to support:
• Ideal for proximity solutions
• Overlay thickness of 15 mm for glass and 5 mm plastic
❐
Superior noise immunity performance against conducted and
radiated noise and ultra low radiated emissions
• Reliable and robust touch performance in noisy environ-
ments
❐
Standardized user modules for overcoming noise
Low power CapSense
®
block with SmartSense™ auto-tuning
❐
Supports a combination of up to 31 buttons or 6 sliders, prox-
imity sensors
❐
Low average power consumption - 28
A
for each sensor at
runtime (wake from sleep and scan sensors every 125 ms)
❐
SmartSense auto-tuning
• Sets and maintains optimal sensor performance during
runtime
• Eliminates system tuning during development and produc-
tion
• Compensates for variations in manufacturing process
Driven shield available on five GPIO pins
❐
Max load of 100 pF at 3 MHz
❐
Frequency range: 375 kHz to 3 MHz
❐
Delivers best-in class water tolerant designs
❐
Robust proximity sensing in the presence of metal objects
Powerful Harvard-architecture processor
❐
M8C CPU with a maximum speed of 24 MHz
❐
Operating range: 1.71 V to 5.5 V
• Standby mode: 1.1 µA (typ)
• Deep sleep: 0.1 µA (typ)
❐
Temperature range: –40 °C to +85 °C
Flexible on-chip memory
❐
8 KB flash, 1 KB SRAM
❐
16 KB flash, 2 KB SRAM
❐
32 KB flash, 2 KB SRAM
❐
50,000 flash erase/write cycles
❐
In-system programming capability
Four clock sources
❐
Internal main oscillator (IMO): 6/12/24 MHz
Internal low-speed oscillator (ILO) at 32 kHz for watchdog
and sleep timers
❐
RC crystal oscillator
❐
Clock input
❐
■
Programmable pin configurations
❐
Up to 32 general-purpose I/Os (GPIOs)
❐
Dual mode GPIO
❐
High sink current of 25 mA for each GPIO. Total 120 mA
maximum sink current per chip
❐
5 mA source current on port 0 and 1 and 1 mA on port 2,3
and 4
❐
Configurable internal pull-up, high-Z, and open drain modes
❐
Selectable, regulated digital I/O on port 1
❐
Configurable input threshold on port 1
Versatile analog mux
❐
Common internal analog bus
❐
Simultaneous connection of I/O
❐
High power supply rejection ratio (PSRR) comparator
❐
Low-dropout voltage regulator for all analog resources
Additional system resources
2
❐
I C slave:
• Selectable to 50 kHz, 100 kHz, or 400 kHz
• Selectable clock stretch or forced Nack mode
• Implementation during sleep modes with less than 100 µA
• I
2
C wake from sleep with hardware address validation
❐
12 MHz SPI master and slave
❐
Three 16-bit timers
❐
Watchdog and sleep timers
❐
Internal voltage reference
❐
Integrated supervisory circuit
❐
10-bit incremental analog-to-digital converter (ADC)
❐
Two general-purpose high speed, low power analog compar-
ators
Complete development tools
❐
Free development tool (PSoC Designer™)
Package options
❐
16-pin SOIC (150 mil)
❐
16-pin QFN – 3 × 3 × 0.6 mm
❐
24-pin QFN – 4 × 4 × 0.6 mm
❐
32-pin QFN – 5 × 5 × 0.6 mm
❐
48-pin QFN – 6 × 6 × 0.6 mm
[1]
❐
30-ball WLCSP
■
■
■
■
■
■
■
■
■
Note
1. Contact your nearest Cypress sales office for details.
Cypress Semiconductor Corporation
Document Number: 001-69257 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised July 3, 2012
CY8C20x37/37S/47/47S/67/67S
Logic Block Diagram
Port 4
Port 3
Port 2
Port 1
Port 0
1.8/2.5/3 V
PWRSYS
[2]
LDO
(Regulator)
PSoC CORE
SYSTEM BUS
Global Analog Interconnect
1K/2 K
SRAM
Interrupt
Controller
Supervisory ROM (SROM)
8K/16K/32 K Flash
Nonvolatile Memory
Sleep and
Watchdog
CPU Core(M8C)
6/12/ 24 MHz Internal Main Oscillator
( IMO)
Internal Low Speed Oscillator ( ILO)
Multiple Clock Sources
CAPSENSE
SYSTEM
Comparator #1
Comparator #2
CapSense
Module
Analog
Reference
Analog
Mux
SYSTEM BUS
I2C
Slave
Internal
Voltage
References
System
Resets
POR
and
LVD
SPI
Master/
Slave
Three 16- Bit
Programmable
Timers
Digital
Clocks
SYSTEM RESOURCES
Note
2. Internal voltage regulator for internal circuitry
Document Number: 001-69257 Rev. *F
Page 2 of 39
CY8C20x37/37S/47/47S/67/67S
Contents
PSoC
®
Functional Overview ............................................ 4
PSoC Core .................................................................. 4
CapSense System ....................................................... 4
Additional System Resources ..................................... 5
Getting Started .................................................................. 5
Application Notes/Design Guides ................................ 5
Development Kits ........................................................ 5
Training ....................................................................... 5
CYPros Consultants .................................................... 5
Solutions Library .......................................................... 5
Technical Support ....................................................... 5
Designing with PSoC Designer ....................................... 6
Select Components ..................................................... 6
Configure Components ............................................... 6
Organize and Connect ................................................ 6
Generate, Verify, and Debug ....................................... 6
Pinouts .............................................................................. 7
16-pin SOIC (12 Sensing Inputs) ................................ 7
16-pin QFN (12 Sensing Inputs) .................................. 8
24-pin QFN (20 Sensing Inputs) .................................. 9
30-ball WLCSP (26 Sensing Inputs) .......................... 10
32-pin QFN (26 Sensing Inputs) ................................ 11
48-pin QFN (33 Sensing Inputs) ................................ 12
Electrical Specifications ................................................ 13
Absolute Maximum Ratings ....................................... 13
Operating Temperature ............................................. 13
DC Chip-Level Specifications .................................... 14
DC GPIO Specifications ............................................ 15
DC Analog Mux Bus Specifications ........................... 17
DC Low Power Comparator Specifications ............... 17
Comparator User Module Electrical Specifications ... 18
ADC Electrical Specifications .................................... 18
DC POR and LVD Specifications .............................. 19
DC Programming Specifications ............................... 19
DC I2C Specifications ............................................... 20
Shield Driver DC Specifications ................................ 20
DC IDAC Specifications ............................................ 20
AC Chip-Level Specifications .................................... 21
AC General Purpose I/O Specifications .................... 22
AC Comparator Specifications .................................. 22
AC External Clock Specifications .............................. 22
AC Programming Specifications ................................ 23
AC I2C Specifications ................................................ 24
Packaging Information ................................................... 27
Thermal Impedances ................................................. 30
Capacitance on Crystal Pins ..................................... 30
Solder Reflow Peak Temperature ............................. 30
Development Tool Selection ......................................... 31
Software .................................................................... 31
Development Kits ...................................................... 31
Evaluation Tools ........................................................ 31
Device Programmers ................................................. 31
Accessories (Emulation and Programming) .............. 32
Third Party Tools ....................................................... 32
Build a PSoC Emulator into Your Board .................... 32
Ordering Information ...................................................... 33
Ordering Code Definitions ......................................... 34
Acronyms ........................................................................ 35
Reference Documents .................................................... 35
Document Conventions ............................................. 35
Units of Measure ....................................................... 35
Numeric Naming ........................................................ 36
Glossary .......................................................................... 36
Document History Page ................................................. 37
Sales, Solutions, and Legal Information ...................... 39
Worldwide Sales and Design Support ....................... 39
Products .................................................................... 39
PSoC Solutions ......................................................... 39
Document Number: 001-69257 Rev. *F
Page 3 of 39
CY8C20x37/37S/47/47S/67/67S
PSoC
®
Functional Overview
The PSoC family consists of many devices with on-chip
controllers. These devices are designed to replace multiple
traditional MCU-based system components with one low-cost
single-chip programmable component. A PSoC device includes
configurable blocks of analog and digital logic, and
programmable interconnect. This architecture makes it possible
for you to create customized peripheral configurations, to match
the requirements of each individual application. Additionally, a
fast central processing unit (CPU), flash program memory,
SRAM data memory, and configurable I/O are included in a
range of convenient pinouts.
The architecture for this device family, as shown in the
Logic
Block Diagram on page 2,
consists of three main areas:
■
■
■
Figure 1. CapSense System Block Diagram
CS1
IDAC
Analog Global Bus
CS2
CSN
Vr
Reference
Buffer
The core
CapSense analog system
System resources
Mux
Comparator
Mux
Cexternal (P0[1]
or P0[3])
A common, versatile bus allows connection between I/O and the
analog system.
Each CY8C20x37/47/67/S PSoC device includes a dedicated
CapSense block that provides sensing and scanning control
circuitry for capacitive sensing applications. Depending on the
PSoC package, up to 34 GPIOs are also included. The GPIOs
provide access to the MCU and analog mux.
Refs
Cap Sense Counters
CSCLK
IMO
CapSense
Clock Select
Oscillator
PSoC Core
The PSoC core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO and
ILO. The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a 4-million instructions per
second (MIPS), 8-bit Harvard-architecture microprocessor.
Analog Multiplexer System
The analog mux bus can connect to every GPIO pin. Pins are
connected to the bus individually or in any combination. The bus
also connects to the analog system for analysis with the
CapSense block comparator.
Switch-control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■
■
■
CapSense System
The analog system contains the capacitive sensing hardware.
Several hardware algorithms are supported. This hardware
performs capacitive sensing and scanning without requiring
external components. The analog system is composed of the
CapSense PSoC block and an internal 1 V or 1.2 V analog
reference, which together support capacitive sensing of up to 31
inputs
[3]
. Capacitive sensing is configurable on each GPIO pin.
Scanning of enabled CapSense pins is completed quickly and
easily across multiple ports.
SmartSense™ Auto-tuning
SmartSense auto-tuning is an innovative solution from Cypress
that removes manual tuning of CapSense applications. This
solution is easy to use and provides robust noise immunity. It is
the only auto-tuning solution that establishes, monitors, and
maintains all required tuning parameters of each sensor during
run time. SmartSense auto-tuning allows engineers to go from
prototyping to mass production without retuning for
manufacturing variations in PCB and/or overlay material
properties.
Complex capacitive sensing interfaces, such as sliders and
touchpads.
Chip-wide mux that allows analog input from any I/O pin.
Crosspoint connection between any I/O pin combinations.
Note
3. 34 GPIOs = 31 pins for capacitive sensing+2 pins for I
2
C + 1 pin for modulator capacitor.
Document Number: 001-69257 Rev. *F
Page 4 of 39
CY8C20x37/37S/47/47S/67/67S
Additional System Resources
System resources provide additional capability, such as
configurable I
2
C slave, SPI master/slave communication
interface, three 16-bit programmable timers, various system
resets supported by the M8C low voltage detection and power-
on reset. The merits of each system resource are listed here:
■
Getting Started
The quickest way to understand PSoC silicon is to read this
datasheet and then use the PSoC Designer Integrated
Development Environment (IDE). This datasheet is an overview
of the PSoC integrated circuit and presents specific pin, register,
and electrical specifications.
For in depth information, along with detailed programming
details, see the
Technical Reference Manual
for the CY8C20x37/
47/67/S PSoC devices.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device datasheets on the web
at
www.cypress.com/psoc.
The I
2
C slave/SPI master-slave module provides 50/100/
400 kHz communication over two wires. SPI communication
over three or four wires runs at speeds of 46.9 kHz to 3 MHz
(lower for a slower system clock).
The I
2
C hardware address recognition feature reduces the
already low power consumption by eliminating the need for
CPU intervention until a packet addressed to the target device
is received.
The I
2
C enhanced slave interface appears as a 32-byte RAM
buffer to the external I
2
C master. Using a simple predefined
protocol, the master controls the read and write pointers into
the RAM. When this method is enabled, the slave does not stall
the bus when receiving data bytes in active mode. For usage
details, see the application note
I2C Enhanced Slave Operation
- AN56007.
Low-voltage detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced power-
on reset (POR) circuit eliminates the need for a system
supervisor.
An internal reference provides an absolute reference for
capacitive sensing.
A register-controlled bypass mode allows the user to disable
the LDO regulator.
■
Application Notes/Design Guides
Application notes and design guides are an excellent
introduction to the wide variety of possible PSoC designs. They
are located at
www.cypress.com/gocapsense.
Select
Application Notes under the Related Documentation tab.
■
Development Kits
PSoC Development Kits are available online from Cypress at
www.cypress.com/shop
and through a growing number of
regional and global distributors, which include Arrow, Avnet, Digi-
Key, Farnell, Future Electronics, and Newark. See
Development
Kits on page 31.
■
■
■
Training
Free PSoC and CapSense technical training (on demand,
webinars, and workshops) is available online at
www.cypress.com/training.
The training covers a wide variety of
topics and skill levels to assist you in your designs.
CYPros Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to
www.cypress.com/cypros.
Solutions Library
Visit our growing library of solution focused designs at
www.cypress.com/solutions.
Here you can find various
application designs that include firmware and hardware design
files that enable you to complete your designs quickly.
Technical Support
For assistance with technical issues, search KnowledgeBase
articles and forums at
www.cypress.com/support.
If you cannot
find an answer to your question, create a technical support case
or call technical support at 1-800-541-4736.
Document Number: 001-69257 Rev. *F
Page 5 of 39
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