INTEGRATED CIRCUITS
DATA SHEET
TDA8575
Ground noise isolation amplifier
Preliminary specification
File under Integrated Circuits, IC01
1996 Jul 29
Philips Semiconductors
Preliminary specification
Ground noise isolation amplifier
FEATURES
•
High common mode rejection up to high frequencies
•
Reduced dependency of common mode rejection on
source resistance
•
Low distortion
•
Low noise
•
AC and DC short-circuit safe
•
Few external components
•
ESD protected on all pins.
GENERAL DESCRIPTION
TDA8575
The TDA8575(T) is a two channel amplifier with differential
input and single-ended output for use in car audio
applications. The differential amplifier has a gain of 0 dB,
a low distortion and a high common mode rejection. The
TDA8575T comes in a 16 pin SO package and TDA8575
comes in a 16 pin DIP package.
The TDA8575(T) is developed for those car audio
applications where long connections between signal
sources and amplifiers (or boosters) are necessary and
ground noise has to be eliminated.
QUICK REFERENCE DATA
SYMBOL
V
CC
I
CC
G
v
V
o(rms)(max)
SVRR
CMRR
THD
V
no
Z
i
Z
o
PARAMETER
supply voltage
supply current
voltage gain
maximum output voltage (RMS value)
supply voltage ripple rejection
common mode rejection ratio
total harmonic distortion
noise output voltage
input impedance
output impedance
R
s
= 0
Ω
THD = 0.1%
V
CC
= 8.5 V
CONDITIONS
5
−
−0.5
−
55
−
−
−
−
V
o(rms)
= 1 V; f = 1 kHz
−
MIN.
TYP.
8.5
12.6
0
1.7
60
80
0.005
3.7
108
−
MAX.
18
15
+0.5
−
−
−
−
5
−
10
UNIT
V
mA
dB
V
dB
dB
%
µV
kΩ
Ω
ORDERING INFORMATION
TYPE
NUMBER
TDA8575T
TDA8575
PACKAGE
NAME
SO16
DIP16
DESCRIPTION
plastic small outline package; 16 leads; body width 3.9 mm
plastic dual in-line package; 16 leads (300 mil); long body
VERSION
SOT109-1
SOT38-1
1996 Jul 29
2
Philips Semiconductors
Preliminary specification
Ground noise isolation amplifier
BLOCK DIAGRAM
TDA8575
handbook, full pagewidth
INL+
1
108
kΩ
12
OUTL
V I
I V
INL−
5
360 kΩ
0.5(VCC
−
0.7)
+
0.7
VCC
0.68(VCC
−
0.7)
+
0.7
16
VCC
8
TDA8575(T)
SVRR
REFERENCE
0.68(VCC
−
0.7)
+
0.7
9
GND
360 kΩ
INR−
6
108
kΩ
V I
I V
0.5(VCC
−
0.7)
+
0.7
INR+
7
11
OUTR
MGE829
Fig.1 Block diagram.
1996 Jul 29
3
Philips Semiconductors
Preliminary specification
Ground noise isolation amplifier
PINNING
SYMBOL
INL+
n.c.
n.c.
n.c.
INL−
INR−
INR+
SVRR
GND
n.c.
OUTR
OUTL
n.c.
n.c.
n.c.
V
CC
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
positive input left
not connected
not connected
not connected
negative input left
negative input right
positive input right
supply voltage ripple rejection
ground
not connected
output voltage right channel
output voltage left channel
not connected
not connected
not connected
supply voltage
DESCRIPTION
TDA8575
handbook, halfpage
INL+
n.c.
n.c.
n.c.
INL−
INR−
INR+
SVRR
1
2
3
4
16 VCC
15 n.c.
14 n.c.
13 n.c.
handbook, halfpage
INL+
n.c.
n.c.
n.c.
INL−
INR−
INR+
SVRR
1
2
3
4
16 VCC
15 n.c.
14 n.c.
13 n.c.
TDA8575T
5
6
7
8
MGE828
TDA8575
12 OUTL
11 OUTR
10 n.c.
9
GND
5
6
7
8
MGE827
12 OUTL
11 OUTR
10 n.c.
9
GND
Fig.2 Pin configuration TDA8575T.
Fig.3 Pin configuration TDA8575.
1996 Jul 29
4
Philips Semiconductors
Preliminary specification
Ground noise isolation amplifier
FUNCTIONAL DESCRIPTION
System description
To enable a high common mode rejection a new system
setup is used. The voltage to current converter, referred to
as V
→
I in the block diagram of Fig.1, replaces the
resistors that can be seen in the conventional system
solution.
Both systems are shown in Figs 4 and 5. In the
conventional system the common mode rejection is limited
by the matching properties of the resistors resulting in a
CMRR of 60 dB maximum. Using the new system setup a
CMRR of 80 dB is achieved.
Power on
In Fig.6 the preferred input capacitor values are shown.
If the capacitor C2 = 22
µF
connected to the IN- inputs had
to be charged by the 0.5V
cc
voltage source a charge time
360 kΩ
of 5τ
=
5
×
------------------
×
22
µF
=
20s would be required.
-
2
TDA8575
This is inconvenient for most applications and therefore
the TDA8575(T) is equipped with a quick charge circuit.
On power-on the quick charge circuit charges the
capacitor C2 connected to the IN- pins. The quick charge
circuit consists of a voltage buffer and a control circuit
(referred to as ‘reference and power check’ in Fig.6) that
monitors the supply voltage V
CC
. If the supply voltage rises
more than
≈
2 V the voltage buffer is switched on.
After charging C2 the voltage buffer is switched off.
The charge time of C2 will equal the charge time of C4, the
SVRR capacitor.
handbook, halfpage
handbook, halfpage
Vi
Vo
Vi
V I
I V
Vo
0.5 VCC
MGE830
0.5 VCC
MGE831
Fig.4 Conventional system.
Fig.5 New system using V
→
I converters.
1996 Jul 29
5
模拟电子
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
