Dual phase-locked loop (PLL) device with three out-
put clock frequencies
3.3V supply voltage
Small circuit board footprint (8-pin 0.150
″
SOIC)
Custom frequency selections available - contact your
local AMI Sales Representative for more information
Figure 1: Pin Configuration
CLKA
VSS
XIN
XOUT
1
8
The FS6282 is a monolithic CMOS clock generator IC
designed to minimize cost and component count in digital
video/audio systems.
Two high-resolution phase-locked loops generate two
output clocks (CLKA and CLKB) through an array of post-
dividers. All frequencies are ratiometrically derived from
the crystal oscillator frequency. The locking of all the out-
put frequencies together can eliminate unpredictable ar-
tifacts in video systems and reduce electromagnetic in-
terference (EMI) due to frequency harmonic stacking.
OE
VDD
CLKC
CLKB
Table 1: Crystal / Output Frequencies
DEVICE
FS6282-03
f
XIN
(MHz) CLKA (MHz) CLKB (MHz) CLKC (MHz)
20.000
20.000
48.000
8.000
FS6282
2
3
4
7
6
5
NOTE: Contact AMI for custom PLL frequencies
8-pin (0.150
″
) SOIC
Figure 2: Block Diagram
XIN
CRYSTAL
OSC.
XOUT
PLL
DIVIDER
ARRAY
CLKA
CLKB
PLL
OE
CLKC
FS6282
This document contains information on a preproduction product. Specifications and information herein are subject to change without notice.
ISO9001
10.1.99
FS6282
Dual PLL Clock Generator IC
AMERICAN MICROSYSTEMS, INC.
October 1999
Table 2: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI
U
= Input with Internal Pull-Up; DI
D
= Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active Low pin
PIN
1
2
3
4
5
6
7
8
TYPE
DO
P
AI
AO
DO
DO
P
DI
U
NAME
CLKA
VSS
XIN
XOUT
CLKB
CLKC
VDD
OE
Clock Output A
Ground
Crystal Oscillator Feedback
Crystal Oscillator Drive
Clock Output B
Clock Output C
Power (+3.3 volts)
DESCRIPTION
Output Enable (outputs active when OE=VDD)
3.0
Electrical Specifications
Table 3: Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at
these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance,
functionality, and reliability.
PARAMETER
Supply Voltage (V
SS
= ground)
Input Voltage, dc
Output Voltage, dc
Input Clamp Current, dc (V
I
< 0 or V
I
> V
DD
)
Output Clamp Current, dc (V
I
< 0 or V
I
> V
DD
)
Storage Temperature Range (non-condensing)
Ambient Temperature Range, Under Bias
Junction Temperature
Lead Temperature (soldering, 10s)
Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7)
SYMBOL
V
DD
V
I
V
O
I
IK
I
OK
T
S
T
A
T
J
MIN.
V
SS
-0.5
V
SS
-0.5
V
SS
-0.5
-50
-50
-65
-55
MAX.
7
V
DD
+0.5
V
DD
+0.5
50
50
150
125
125
260
2
UNITS
V
V
V
mA
mA
°C
°C
°C
°C
kV
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy elec-
trostatic discharge.
Table 4: Operating Conditions
PARAMETER
Supply Voltage
Ambient Operating Temperature Range
SYMBOL
V
DD
T
A
CONDITIONS/DESCRIPTION
3.3V ± 10%
MIN.
3.0
0
TYP.
3.3
MAX.
3.6
70
UNITS
V
°C
2
ISO9001
10.1.99
FS6282
AMERICAN MICROSYSTEMS, INC.
Dual PLL Clock Generator IC
October 1999
Table 5: DC Electrical Specifications
Unless otherwise stated, V
DD
= 3.3V ± 10%, no load on any output, and ambient temperature range T
A
= 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are
±
3σ f rom typical. Negative currents indicate current flows out of the device.
PARAMETER
Overall
Supply Current, Dynamic, with Loaded
Outputs
Crystal Oscillator
Crystal Loading Capacitance
Clock Outputs (CLKA, CLKB)
Output Impedance *
Short Circuit Source Current *
Short Circuit Sink Current *
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
I
DD
f
XTAL
= 13.5MHz; C
L
= 10pF, V
DD
= 3.6V
30
mA
C
L(xtal)
As seen by a crystal connected to XIN and
XOUT
18
pF
z
OH
z
OL
I
OSH
I
OSL
V
O
= 0.1V
DD
; output driving high
V
O
= 0.1V
DD
; output driving low
V
O
= 0V; shorted for 30s, max.
V
O
= 3.3V; shorted for 30s, max.
45
45
-35
35
Ω
mA
mA
Table 6: AC Timing Specifications
Unless otherwise stated, V
DD
= 3.3V ± 10%, no load on any output, and ambient temperature range T
A
= 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are
±
3σ f rom typical.
PARAMETER
Overall
Synthesis Error
Clock Outputs (CLKA, CLKB, CLKC)
Duty Cycle *
Jitter, Period (peak-peak) *
Rise Time *
Fall Time *
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
(unless otherwise noted in Frequency Table)
0
ppm
Ratio of high pulse width (as measured from rising edge to next falling
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