The FS6261-01 is a CMOS clock generator IC designed
for high-speed motherboard applications. Two different
frequencies can be selected for the CPU clocks via two
SEL pins. Glitch-free stop clock control of the CPU, AGP
(66MHz) and PCI clocks is provided. A low current
power-down mode is available for mobile applications.
Separate clock buffers provide for a 2.5V voltage range
on the CPU_0:3, CPU/2_0:1 and APIC_0:2 clocks.
Figure 2: Pin Configuration
VSS_R
REF_0
REF_1
VDD_R
XIN
XOUT
VSS_P
PCI_F
PCI_1
VDD_P
PCI_2
PCI_3
VSS_P
PCI_4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDD_A
APIC_2
APIC_1
APIC_0
VSS_A
VDD_C2
CPU/2_1
CPU/2_0
VSS_C2
VDD_C
CPU_3
CPU_2
VSS_C
VDD_C
CPU_1
CPU_0
VSS_C
VDD
VSS
PCI_STOP#
CPU_STOP#
PWR_DWN#
SS_EN#
SEL_1
SEL_0
VDD_48
CK48
VSS_48
CPU clock cycle – cycle jitter < 150ps p-p
Non-linear spread-spectrum modulation
(-0.5% at 31.5kHz)
Supports test mode and tristate output control
Separate CPU-enable, PCI-enable and power-down
inputs with glitch-free stop clock controls on all clocks
for clock control and power management
(2.5V outputs)
FS6261-01
Figure 1: Block Diagram
XIN
XOUT
Crystal
Oscillator
VDD_R
PCI_5
VDD_P
PCI_6
PCI_7
VSS_P
VSS_66
CK66_0
VDD_C2
REF_0:1
SEL_0:1
SS_EN#
SEL_133/100#
VSS_R
PLL
÷2
CPU/2_0:1
VSS_C2
VDD_A
CK66_1
VDD_66
VSS_66
CK66_2
CK66_3
VDD_66
SEL133/100#
delay
PWR_DWN#
÷6 or
÷8
APIC_0:2
VSS_A
VDD_C
CPU_0:3
VSS_C
(2.5V outputs)
56-pin SSOP
CPU_STOP#
VDD_66
delay
÷1½
or ÷2
Table 1: CPU/PCI Frequency Selection
SEL_133/100#
0
0
0
0
1
1
1
1
SEL_1
0
0
1
1
0
0
1
1
SEL_0
0
1
0
1
0
1
0
1
CPU (MHz)
tristate
(reserved)
100
100
XIN/2
(reserved)
133
133
PCI (MHz)
tristate
(reserved)
33.33
33.33
XIN/6
(reserved)
33.33
33.33
CK66_0:3
VSS_66
VDD_P
delay
PCI_STOP#
÷3 or
÷4
PCI_F
PCI_1:7
VSS_P
VDD_48
PLL
÷3 or
÷4
CK48
VSS_48
FS6261-01
Intel and Pentium are registered trademarks of Intel Corporation. Spread spectrum modulation is licensed under US Patent No. 5488627, Lexmark International, Inc. American Microsystems, Inc.
reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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Table 2: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI
U
= Input with Internal Pull-Up; DI
D
= Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active-low pin
PIN
53, 54, 55
30
21, 22, 25, 26
41, 42, 45, 46
49, 50
36
9, 11, 12, 14,
15, 17, 18
8
37
35
2, 3
32, 33
28
34
39
31
23, 27
56
43, 47
51
10, 16
4
38
29
20, 24
52
40, 44
48
7, 13, 19
1
5
6
TYPE
DO
DO
DO
DO
DO
DI
U
DO
DO
DI
U
DI
U
DO
DI
U
NAME
APIC_0:2
CK48
CK66_0:3
CPU_0:3
CPU/2_0:1
CPU_STOP#
PCI_1:7
PCI_F
PCI_STOP#
PWR_DWN#
REF_0:1
SEL_0:1
SEL_133/100#
SS_EN#
VDD
VDD_48
VDD_66
VDD_A
VDD_C
VDD_C2
VDD_P
VDD_R
VSS
VSS_48
VSS_66
VSS_A
VSS_C
VSS_C2
VSS_P
VSS_R
XIN
XOUT
DESCRIPTION
Three low-skew (<250ps @ 1.25V) 2.5V 16.67MHz clock outputs for APIC bus timing. APIC
clocks are synchronous with CPU clocks but lag the CPU clocks by 1.5 to 4ns.
One 3.3V 48MHz clock output for Universal Serial Bus (USB) timing
Four 3.3V 66MHz AGP clock outputs. CK66 clocks are synchronous with CPU clocks but lag the
CPU clocks by 0 to 1.5ns.
Four low-skew 2.5V 133/100MHz CPU clock outputs for host frequencies
Two low-skew 2.5V clock outputs at half the CPU clock frequencies (66/50MHz)
CPU_0:3 and CK66_0:3 clock output enable. Asynchronous, active-low disable stops all CPU
and CK66 clocks in the low state.
Seven 3.3V PCI clock outputs. PCI clocks are synchronous with CPU clocks but lag the CK66
clocks by 1.5 to 4ns.
One free-running 3.3V PCI clock output
PCI_1:7 clock output enable. Asynchronous, active-low disable stops all PCI clocks in the low
state.
Asynchronous active-low power-down signal shuts down oscillator, all PLLs, puts all clocks in
low state. Clock re-enable latency of
≤
3ms.
Two buffered outputs of the 14.318MHz reference clock
Two frequency select inputs (see Table 4)
Selects 133MHz or 100MHz CPU frequency (pull-up/pull-down
must
be provided externally)
Spread spectrum enable. Active-low enable turns on the spread spectrum feature; a logic-high
turns off the spread spectrum modulation.
3.3V ± 10%
Power supply for 3.3V CK48 clock output
Power supply for 3.3V CK66_0:3 clock outputs
Power supply for 2.5V APIC_0:2 clock outputs
Power supply for 2.5V CPU_0:3 clock outputs
Power supply for 2.5V CPU/2_0:1 clock outputs
Power supply for 3.3V PCI_1:7 and PCI_F clock outputs
Power supply for 3.3V REF_0:1 clock outputs
Ground
Ground for CK48 clock outputs
Ground for CK66_0:3 clock outputs
Ground for APIC_0:2 clock outputs
Ground for CPU_0:3 clock outputs
Ground for CPU/2_0:1 clock outputs
Ground for PCI_1:7 and PCI_F clock outputs
Ground for REF_0:1 clock outputs
14.318MHz crystal oscillator input. XIN can be driven by an external frequency source.
14.318MHz crystal oscillator output
DI
DI
U
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
AI
AO
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Table 3: Actual Clock Frequencies
Note: Spread spectrum disabled
CLOCK
APIC_0:2
CPU_0:3
CPU/2_0:1
PCI_1:7, PCI_F
CK66_0:3
CK48
(1)
TARGET (MHz)
16.67 (with CPU = 133.3)
16.67 (with CPU = 100.0)
133.33
100.00
66.67
50.00
33.33 (with CPU = 133.3)
33.33 (with CPU = 100.0)
66.67 (with CPU = 133.3)
66.67 (with CPU = 100.0)
48
ACTUAL (MHz)
16.6634
16.6661
133.3072
99.9963
66.6536
49.9982
33.3268
33.3321
66.6536
66.6642
48.0080
DEVIATION (ppm)
-195.92
-36.657
-195.92
-36.657
-195.92
-36.657
-195.92
-36.657
-195.92
-36.657
+167
(1) 48MHz USB clock is required to be 167ppm off from 48.000MHz to conform to USB requirements.
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