C is a licensed trademark of Philips Electronics, N.V. Windows and Windows NT are registered trademarks of Microsoft Corporation. American Microsystems, Inc. reserves the right to change detail
specifications as may be required to permit improvements in the design of its products.
FS6131-01
Programmable Line Lock Clock Generator IC
Table 1: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI
U
= Input with Internal Pull-Up; DI
D
= Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active Low pin
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TYPE
DI
DIO
DI
P
AI
AO
AI
P
DIO
AI
P
DI
DI
P
DO
DO
NAME
SCL
SDA
ADDR
VSS
XIN
XOUT
XTUNE
VDD
LOCK/IPRG
EXTLF
VSS
REF
FBK
VDD
CLKP
CLKN
DESCRIPTION
Serial Interface Clock (requires an external pull-up)
Serial Interface Data Input/Output (requires an external pull-up)
Address Select Bit (see Section 5.2.1)
Ground
VCXO Feedback
VCXO Drive
VCXO Tune
Power Supply (+5V)
Lock Indicator / PECL Current Drive Programming
External Loop Filter
Ground
Reference Frequency Input
Feedback Input
Power Supply (+5V)
Differential Clock Output (+)
Differential Clock Output (-)
4.0
4.1
Functional Block Description
Main Loop PLL
frequency appearing at the inputs of the PFD are equal.
The input/output relationship between the reference fre-
quency and the VCO frequency is
The Main Loop Phase Locked Loop (ML-PLL) is a stan-
dard phase- and frequency- locked loop architecture. As
shown in Figure 2, the ML-PLL consists of a Reference
Divider, a Phase-Frequency Detector (PFD), a charge
pump, an internal loop filter, a Voltage-Controlled Oscil-
lator (VCO), a Feedback Divider, and a Post Divider.
During operation, the reference frequency (f
REF
), gener-
ated by either the on-board crystal oscillator or an exter-
nal frequency source, is first reduced by the Reference
Divider. The integer value that the frequency is divided by
is called the modulus, and is denoted as N
R
for the Ref-
erence Divider. The divided reference is then fed into the
PFD.
The PFD controls the frequency of the VCO (f
VCO
)
through the charge pump and loop filter. The VCO pro-
vides a high-speed, low noise, continuously variable fre-
quency clock source for the ML-PLL. The output of the
VCO is fed back to the PFD through the Feedback Di-
vider (the modulus is denoted by N
F
) to close the loop.
The PFD will drive the VCO up or down in frequency until
the divided reference frequency and the divided VCO
2
f
VCO
f
=
REF
.
N
F
N
R
If the VCO frequency is used as the PLL output fre-
quency (f
CLK
) then the basic PLL equation can be rewrit-
ten as
æ
N
ö
f
CLK
=
f
REF
ç
F
÷
.
ç
N
÷
è
R
ø
4.1.1
Reference Divider
The Reference Divider is designed for low phase jitter.
The divider accepts either the output of either the Crystal
Loop (the VCXO output) or an external reference fre-
quency, and provides a divided-down frequency to the
PFD. The Reference Divider is a 12-bit divider, and can
be programmed for any modulus from 1 to 4095. See
both Table 3 and Table 8 for additional programming in-
formation.
FS6131-01
Programmable Line Lock Clock Generator IC
4.1.2
Feedback Divider
The Feedback Divider is based on a dual-modulus
prescaler technique. The technique allows the same
granularity as a fully programmable feedback divider,
while still allowing the programmable portion to operate at
low speed. A high-speed pre-divider (also called a
prescaler) is placed between the VCO and the program-
mable Feedback Divider because of the high speeds at
which the VCO can operate. The dual-modulus technique
insures reliable operation at any speed that the VCO can
achieve and reduces the overall power consumption of
the divider.
For example, a fixed divide-by-eight could be used in the
Feedback Divider. Unfortunately, a divide-by-eight would
limit the effective modulus of the feedback divider path to
multiples of eight. The limitation would restrict the ability
of the PLL to achieve a desired input-frequency-to-
output-frequency ratio without making both the Reference
and Feedback Divider values comparatively large. Large
divider moduli are generally undesirable due to increased
phase jitter.
4.1.3
Feedback Divider Programming
The requirement that M≥A means that the Feedback Di-
vider can only be programmed for certain values below a
divider modulus of 56. The selection of divider values is
listed in Table 2.
If the desired Feedback Divider is less than 56, find the
divider value in the table. Follow the column up to find the
A-counter program value. Follow the row to the left to find
the M-counter value.
Above a modulus of 56, the Feedback Divider can be
programmed to any value up to 16383. See both Table 3
and Table 8 for additional programming information.
Table 2: Feedback Modulus Below 56
M-COUNTER:
FBKDIV[13:3]
00000000001
00000000010
00000000011
A-COUNTER: FBKDIV[2:0]
000
8
16
24
32
40
48
56
001
9
17
25
33
41
49
57
010
-
18
26
34
42
50
58
011
-
-
27
35
43
51
59
100
-
-
-
36
44
52
60
101
-
-
-
-
45
53
61
110
-
-
-
-
-
54
62
111
-
-
-
-
-
-
63
Figure 3: Feedback Divider
f
vco
Dual-
Modulus
Prescaler
M
Counter
00000000100
00000000101
00000000110
00000000111
FEEDBACK DIVIDER MODULUS
A
Counter
To understand the operation, refer to Figure 3. The M-
counter (with a modulus of M) is cascaded with the dual-
modulus prescaler. If the prescaler modulus were fixed at
N, the overall modulus of the feedback divider chain
would be M×N. However, the A-counter causes the
prescaler modulus to be altered to N+1 for the first A out-
puts of the prescaler. The A-counter then causes the
dual-modulus prescaler to revert to a modulus of
N
until
the M-counter reaches its terminal state and resets the
entire divider. The overall modulus can be expressed as
A
(
N
+
1)
+
N
(
M
−
A
)
,
where M
≥
A, which simplifies to
4.1.4
Post Divider
The Post Divider consists of three individually program-
mable dividers, as shown in Figure 4.
Figure 4: Post Divider
POST1[1:0]
POST2[1:0]
POST3[1:0]
f
GBL
Post
Divider 1
(N
P1
)
Post
Divider 2
(N
P2
)
POST DIVIDER (N
Px
)
Post
Divider 3
(N
P3
)
f
out
M
×
N
+
A
.
The moduli of the individual dividers are denoted as N
P1
,
N
P2
, and N
P3
, and together they make up the array
modulus N
Px
.
N
Px
=
N
P
1
×
N
P
2
×
N
P
3
3
FS6131-01
Programmable Line Lock Clock Generator IC
The Post Divider performs several useful functions. First,
it allows the VCO to be operated in a narrower range of
speeds compared to the variety of output clock speeds
that the device is required to generate. Second, it
changes the basic PLL equation to
æ
N
öæ
1
ö
f
CLK
=
f
REF
ç
F
֍
ç
N
֍
N
÷
.
÷
è
R
øè
Px
ø
The extra integer in the denominator permits more flexi-
bility in the programming of the loop for many applica-
tions where frequencies must be achieved
exactly.
Note that a nominal 50/50 duty factor is preserved for
selections which have an odd modulus.
4.2.1
Clock Gobbler (Phase Adjust)
The Clock Gobbler circuit takes advantage of the un-
known relationship between input and output clocks to
permit the adjustment of the CLKP/CLKN output clock
phase relative to the REF input. The Clock Gobbler circuit
removes a VCO clock pulse before the pulse clocks the
Post Divider. In this way, the phase of the output clock
can be slipped until the output phase is aligned with the
input clock phase.
To adjust the phase relationship, switch the Feedback
Divider source to the Post Divider input via the
FBKDSRC bit, and toggle the GBL register bit. The Clock
Gobbler output clock is delayed by one VCO clock period
for each transition of the GBL bit from zero to one.
4.2.2
Phase Alignment
To maintain a fixed phase relation between input and
output clocks, the Post Divider must be placed inside the
feedback loop. The source for the Feedback Divider is
obtained from the output of the Post Divider via the
FBKDSRC switch. In addition, the Feedback Divider must
be dividing at a multiple of the Post Divider.
4.2
Phase Adjust and Sampling
In line-locked or genlocked applications, it is necessary to
know the exact phase relation of the output clock relative
to the input clock. Since the VCO is included within the
feedback loop in a simple PLL structure, the VCO output
is exactly phase aligned with the input clock. Every cycle
of the input clock equals N
R
/N
F
cycles of the VCO clock.
Figure 5: Simple PLL
f
IN
Reference
Divider (N
R
)
Figure 7: Aligned I/O Phase
Phase
Frequency
Detect
VCO
f
OUT
f
IN
Reference
Divider (N
R
)
f
IN
f
OUT
Phase
Frequency
Detect
VCO
Post
Divider (N
F
)
f
OUT
Feedback
Divider (N
F
)
f
IN
f
OUT
Feedback
Divider (N
F
)
The addition of a Post Divider, while adding flexibility,
makes the phase relation between the input and output
clock unknown because the Post Divider is outside the
feedback loop.
Figure 6: PLL with Post Divider
f
IN
Reference
Divider (N
R
)
Phase
Frequency
Detect
VCO
Post
Divider (N
F
)
f
OUT
f
IN
f
VCO
f
OUT
?
Feedback
Divider (N
F
)
f
VCO
4.2.3
Phase Sampling and Initial Alignment
However, the ability to adjust the phase is useless with-
out knowing the initial relation between output and input
phase. To aid in the initial synchronization of the output
phase to input phase, a Phase Align “flag” makes a tran-
sition (zero to one or one to zero) when the output clock
phase becomes aligned with the feedback source phase.
The feedback source clock is, by definition, locked to the
input clock phase.
First, the FS6131 is used to sample the output clock with
the feedback source clock and set/clear the Phase Align
flag when the two clocks match to within a feedback
source clock period. Then, the Clock Gobbler is used to
delay the output phase relative to the input phase one
VCO clock at a time until a transition on the flag occurs.
When a transition occurs, the output and input clocks are
phase aligned.
4
FS6131-01
Programmable Line Lock Clock Generator IC
To enter this mode, set STAT[1] to one and clear
STAT[0] to zero. If the CMOS bit is set to one, the
LOCK/IPRG pin can display the flag. The flag is always
available under software control by reading back the
STAT[1] bit, which will be overwritten by the flag in this
mode.
4.2.4
Feedback Divider Monitoring
The Feedback Divider clock can be brought out the
LOCK/IPRG pin independent of the output clock to allow
monitoring of the Feedback Divider clock. To enter this
mode, set both the STAT[1] and STAT[0] bits to one. The
CMOS bit must also be set to one to enable the
LOCK/IPRG pin as an output.
The VCO transfer function (in rad/s, and accounting for
the phase integration that occurs in the VCO) is:
K
VCO
(
s
)
=
2
π
A
VCO
1
s
The transfer function of the Feedback Divider is:
K
F
=
1
N
F
Finally, the sampling effect that occurs in the Phase De-
tector is accounted for by:
ö
−
æ
s f
æ
ç
÷
è
REF
ø
ç
1
−
e
K
SAMP
(
s
)
=
ç
s
ç
è
4.3
Loop Gain Analysis
ö
÷
÷
f
REF
÷
ø
For applications where an external loop filter is required,
the following analysis example can be used to determine
loop gain and stability.
The loop gain of a PLL is the product of all of the gains
within the loop.
Establish the basic operating parameters:
Set the charge pump current:
The loop gain of the PLL is:
K
LOOP
(
s
)
=
K
PD
K
LF
(
s
)
K
VCO
(
s
)
K
F
K
SAMP
(
s
)
Figure 8: Loop Gain vs. Frequency
100
I
chgpump
=
10
µ
A
R
LF
=
15
k
Ω
Set the loop filter values:
C
1
=
0.015
µ
F
C
2
=
220
pF
10
Set the VCO gain (VCOSPD):
Set the Feedback Divider:
N
F
=
3500
Amplitude
A
VCO
=
230
MHz
/
V
1
Set the Reference frequency (at the input to the Phase
Detector:
f
REF
=
20
kHz
The transfer function of the Phase Detector and Charge
Pump combination is (in A/rad):
0.1
K
PD
=
I
chgpump
2
π
1
0.01
0.1kHz
1kHz
10kHz
100kHz
The transfer function of the loop filter is (in V/A):
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
