Advance Information
CAT24C21
1K (128 x 8) -Bit Dual Mode Serial EEPROM for VESA Plug and Play
FEATURES
s
400 kHz I
2
C bus compatible*
s
DDC1
TM
/DDC2
TM
interface compliant for
s
16-byte page write buffer
LEAD-FREE
PACKAGE
OPTION
s
Self-timed write cycle with auto-clear
s
1,000,000 program/erase cycles
s
100 year data retention
s
8-pin DIP, SOIC, TSSOP or MSOP packages
s
Commercial, industrial and extended
monitor identification
s
2.5 to 6.0 volt operation
s
Low power CMOS technology
s
Write protect feature
— Entire array protected when VCLK at V
IL
temperature ranges
DESCRIPTION
The CAT24C21 is a 1k-bit Serial CMOS EEPROM
internally organized as 128 words of 8 bits each. The
CAT24C21 can operate in two modes compliant to the
VESA, DDC1
TM
and DDC2
TM
standards for "Plug and
Play" monitors. The Transmit-only Mode controlled by
the VCLK input and the bi-directional Mode where the
memories content is controlled by the I
2
C bus, SCL
input. Catalyst’s advanced CMOS technology
substantially reduces device power requirements. The
CAT24C21 features a 16-byte page write buffer. The
device operates via the I
2
C bus serial interface, has a
special write protection feature, and is available in 8-pin
DIP, SOIC, TSSOP and MSOP packages.
PIN CONFIGURATION
DIP Package (P, L)
NC
NC
NC
VSS
1
2
3
4
8
7
6
5
VCC
VCLK
SCL
SDA
BLOCK DIAGRAM
SOIC Package (J, W)
NC
NC
NC
VSS
1
2
3
4
8
7
6
5
VCC
VCLK
SCL
SDA
EXTERNAL LOAD
DOUT
ACK
VCC
VSS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
SENSE AMPS
SHIFT REGISTERS
MSOP Package (R, Z)
NC
NC
NC
VSS
1
2
3
4
8
7
6
5
VCC
VCLK
SCL
SDA
TSSOP Package (U, Y)
SDA
NC
NC
NC
VSS
1
2
3
4
8
7
6
5
VCC
VCLK
SCL
SDA
START/STOP
LOGIC
XDEC
SCL
CONTROL
LOGIC
EEPROM
PIN FUNCTIONS
Pin Name
NC
SDA
SCL
VCLK
V
CC
V
SS
Function
No Connect
Serial Data/Address
Serial Clock (Bidirectional Mode)
Serial Clock (Transmit only Mode)
+2.5V to +6.0V Power Supply
Ground
VCLK
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I
2
C Bus Protocol.
© 2002 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1032, Rev. B
CAT24C21
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias .................. -55°C to +125°C
Storage Temperature ........................ -65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(1)
............ -2.0V to +V
CC
+ 2.0V
V
CC
with Respect to Ground ................ -2.0V to +7.0V
Package Power Dissipation
Capability (TA = 25°C) .................................. 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)
T
DR(3)
V
ZAP(3)
I
LTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-up
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
2000
100
Max
Units
Cycles/Byte
Years
Volts
mA
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +6.0V, unless otherwise specified.
Symbol
I
CC
I
SB(5)
I
LI
I
LO
V
IL
V
IH
V
OL1
V
OL2
V
IL
V
IH
Parameter
Power Supply Current
Standby Current (V
CC
= 5.0V)
Input Leakage Current
Output Leakage Current
Input Low Voltage (SCL & SDA)
Input High Voltage (SCL & SDA)
Output Low Voltage (V
CC
= 3.0V)
Output Low Voltage (V
CC
= 1.8V)
Input Low Voltage (VCLK)
Input High Voltage (VCLK)
Test Conditions
f
SCL
= 100 KHz
V
IN
= GND or V
CC
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
Min
Typ
Max
3
0
10
10
Units
mA
µA
µA
µA
V
V
V
V
V
V
–1
V
CC
x 0.7
I
OL
= 3 mA
I
OL
= 1.5 mA
2.0
V
CC
x 0.3
V
CC
+ 0.5
0.4
0.5
V
CC
x 0.2
0.8
CAPACITANCE
T
A
= 25°C, f = 1.0 MHz, V
CC
= 5V
Symbol
C
I/O(3)
C
IN(3)
Test
Input/Output Capacitance (SDA)
Input Capacitance (VCLK, SCL)
Conditions
V
I/O
= 0V
V
IN
= 0V
Min
Typ
Max
8
6
Units
pF
pF
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+ 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
(5) Standby Current (I
SB
) = 0µA (<900nA).
Doc. No. 1032, Rev. B
2
CAT24C21
A.C. CHARACTERISTICS
V
CC
= +1.8V to +6.0V, unless otherwise specified.
Transmit-only Mode
Symbol
TVAA
TVHIGH
TVLOW
TVHZ
TUPV
Parameter
Output valid from VCLK
VCLK high
VCLK low
Mode transition
Transmit-only power-up
Min
0.6
1.3
2.5V to 6.0V
Typ
Max
0.5
Units
µs
µs
µs
0.5
0
µs
ns
Read & Write Cycle Limits
Symbol
Parameter
Min
F
SCL
T
I(1)
t
AA
t
BUF(1)
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R(1)
t
F(1)
t
SU:STO
t
DH
Clock Frequency
Noise Suppression Time
Constant at SCL, SDA Inputs
SCL Low to SDA Data Out
and ACK Out
Time the Bus Must be Free Before
a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
0.6
100
1.2
0.6
1.2
0.6
0.6
0
50
2.5V-6.0V
Typ
Max
400
200
1
Units
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
0.3
300
µs
ns
µs
ns
Power-Up Timing
(1)(2)
Symbol
t
PUR
t
PUW
Write Cycle Limits
Symbol
t
WR
Parameter
Write Cycle Time
Min.
Typ
Max
10
Units
ms
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max
1
1
Units
ms
ms
The write cycle time is the time from a valid stop condition
of a write sequence to the end of the internal program/
erase cycle. During the write cycle, the bus interface
circuits are disabled, SDA is allowed to remain high, and
the device does not respond to its slave address.
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
3
Doc. No. 1032, Rev. B
CAT24C21
FUNCTIONAL DESCRIPTION
The CAT24C21 has two modes of operation: the Trans-
mit-only Mode and the Bi-directional Mode. There is a
separate 2-wire protocol to support each mode; each
having a separate clock input (SCL and VCLK) and both
modes sharing a common Bi-directional data line (SDA).
The CAT24C21 enters the transmit-only mode upon
power up and begins outputting data on the SDA pin with
each clock signal on the VCLK pin. The device will
remain in the transmit-only mode until there is a valid
high to low transition on the SCL pin. The device will
switch into the bi-directional mode when there is a valid
transition on the SCL pin. Once in the bi-directinal mode,
the only way to return to the transmit-only mode is by
powering down the device.
Transmit-only Mode: (DDC1)
The CAT24C21 will power up in the Transmit-only mode
Figure 1. Transmit-only Mode
and output one bit of data on the SDA pin for each rising
edge of the VCLK pin. Data is transmitted in 8 bit words
with the most significant bit first followed by a 9th "don't
care" bit which will be in the high impedance state. The
CAT24C21 will continuously sequence through the entire
memory array as long as VCLK is present and no falling
edges on SCL are received. When the maximum address
(7FH) is reached, the output will wrap around to the zero
location (00H) and continue. The bi-directional mode
clock (SCL) pin must be held high for the device to
remain in the transmit-only mode.
Upon power-up, the CAT24C21 will output valid data
only after it has been initialized. During initialization,
data will not be available until after the first nine clocks
are sent to the device. The starting address for the
transmit-only mode can be determined during
initialization. If the SDA pin is low during the first eight
clocks, the starting address will be 7FH. If the SDA pin
SCL must remain high for transmit-only mode
SCL
Bit8
(MSB)
Bit1
(LSB)
Don't
Care
SDA
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit8
Bit7
VCLK
TVHIGH
TVLOW
Figure 2. Device Initialization for Transmit-only Mode
SCL
SDA
SDA at high impedance for 9 clock cycles
Bit8
Bit7
Bit6
Bit5
Bit4
VCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
TVPU
TVAA
Figure 3. Mode Transition
Transmit-Only Mode
SCL
TVHZ
Bi-Directional Mode
SDA
VCLK
Doc. No. 1032, Rev. B
4
CAT24C21
is low during the first eight clocks, the starting address
will be 00H. During the ninth clock, SDA will be in the high
impedance state.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
When in the Bi-directional mode, all inputs to the VCLK
pin are ignored, except when a logic high is required to
enable write capability.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24C21 monitors the
SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
PIN DESCRIPTIONS
SCL:
Serial Clock
The CAT24C21 serial clock input pin is used to clock all
data transfers into or out of the device when in the
bi-directional mode.
SDA:
Serial Data/Address
The CAT24C21 bi-directional serial data/address pin is
used to transfer data into and out of the device. The SDA
pin is an open drain output and can be wire-ORed with
other open drain or open collector outputs.
VCLK:
Serial Clock
The VCLK serial clock input pin is used to clock data out
of the device when in transmit-only mode.
BI-DIRECTIONAL MODE (DDC2)
The following defines the features of the I
2
C bus protocol
when in the bi-directional mode:
(1) Data transfer may be initiated only when the bus is
not busy.
Figure 4. Bus Timing
tF
tLOW
SCL
tSU:STA
tHD:STA
tHD:DAT
tHIGH
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master then sends the address
of the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are fixed
tR
tLOW
tSU:DAT
tSU:STO
SDA IN
tAA
SDA OUT
tDH
tBUF
Figure 5. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
5
Doc. No. 1032, Rev. B
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