UTOPIA.I.O
1 TO 4
(128 X 9 X 4)
DEMULTIPLEXER-.I.O
.eatures:
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1,6%%!
General Description
The IDT77301 UtopiaFIFO is a high-speed, low power single input
port supplying four demultiplexing FIFO output ports. Each of the four
output synchronous (clocked) FIFOs are 64 words (128 bytes) in depth.
Data is written to the input port in “cells” (fixed length data packets). The
cell size is programmable from 16 bytes to 128 bytes.
The input port can be configured to support 9-bit or 18-bit wide data
buses. (Multiple 77301’s can be configured to handle 32 and 64-bit buses
with no additional logic.)
There are four routing methods that can be used to transfer data to the
77301. Two methods use out-band routing for the port selection, which
requires use of the Address Location bus. The remaining two methods
support in-band routing, which uses the Address Location bus in conjunc-
tion with the Data bus for port selection. Utopia 2 signaling supports single
cell transfers to single output ports, but the 77301 also offers a proprietary
multicasting protocol. Multicasting enables a single cell to be transferred
simultaneously to multiple selected output ports.
The four output ports can be configured as 9-bit or 4-bit wide data
buses. (18-bit wide buses can be supported with multiple 77301’s with no
Data transfers on fixed cell sizes
Programmable cell size
One input port to four output ports
Four Independent output 128 x 9 FIFO Queues
Selectable eighteen bit or nine bit input bus
Selectable eight/nine bit or four bit output buses
Programmable chip Identification
“UtopiaTx” level 2 compliant input interface signaling
“UtopiaTx” level 1 compliant output interface signaling
Separate clocks for input and output
Selectable In-band or Out-band routing
Multicast capability
Data clock rates to 62.5 MHz, 10ns access time
Building Block Implementation allows up to 32 output channels with
a 18, 36 or 64-bit input bus
Four 562 Mbps output channels can be derived from a single
1.1256 Gbps input channel with no additional glue logic
100-pin TQPF package
.unctional Block Diagram
128 BYTE
FIFO
RMS
MAS
BSS
ADR (0-4)
SOCR
SOCS - a
ENS
- a
CLAVS - a
Data - a (D0-D8)
SOCS - b
ENS
- b
CLAVS - b
Data - b (D0-D8)
SOCS - c
ENS
- c
CLAVS - c
Data - c (D0-D8)
SOCS - d
ENS
- d
CLAVS - d
Data - d (D0-D8)
128 BYTE
FIFO
ENR
CLAVR
Data (D0-D17)
WCLK
128 BYTE
FIFO
128 BYTE
FIFO
RST
MSE
BNE
CONTROL
REGISTER
RCLK
SLE
SCLK
SDI/P_ID0
3240 drw 01
OE
MARCH 2001
1
©2001 Integrated Device Technology, Inc.
DSC-3240/3
IDT77301
UtopiaFIFO™ 1 to 4 (128 x 9 x 4) Demultiplexer-FIFO
Commercial and Industrial Temperature Ranges
additional logic required.) Utopia 1 signalling protocol is supported for
these ports. Data can be read from each FIFO output port independently.
Separate input and output port clocks are provided and can be
operated up to 62.5 MHz. This provides the user with 1.125Gbps
composite bandwidth on the input port and 562Mbps bandwidth on each
output port.
Each 77301 has a unique programmable chip identification register.
Multiple UtopiaFIFOs with programmed chip identification can be utilized
to direct a 9, 18, 36 or 64-bit bus to as many as 31 output ports.
The principle application for the 77301 is in ATM networking based
systems, but can be used in any cell based data or telecommunications
application requiring the separation of independent data streams from a
single input channel.
.unctional Description
The signaling mode of operation is Utopia Transmit (UtopiaTx). With
UtopiaTx, data transfer is initiated by the device able to receive a cell by
asserting the TxCLAV (cell space available, CLAVR for the input port of
the 77301). The device sending data responds, if a cell is available for
transfer, by asserting the enable, TxENB (ENR and
ENS
for the 77301).
During the first byte transfer the TxSOC is asserted to identify the beginning
of the cell transfer. Successive clocks transfer the cell until the last data
transfer. The transfer can only be interrupted by the transmitting agent by
deasserting the TxENB signal. Once reasserted, the process will continue.
Upon completion of the last byte transfer, the condition for additional
transfers is determined by the TxCLAV and TxENB as before. This is
described in greater detail in the Utopia ATM-PHY Level 2 version 1
Document.
Pin Confituration
ENS
a
CLAVSa
GND
SOCSa
Data a 8
Data a 7
Data a 6
Data a 5
Vcc
Data a 4
Data a 3
Data a 2
Data a 1
Data a 0
GND
RCLK
SDI/P_ID0
SCLK
Data b 0
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
SLE
OE
MSE
RMS
MAS
BNE
Data b 1
Data b 2
Vcc
Data b 3
Data b 4
Data b 5
Data b 6
Data b 7
GND
Data b 8
SOCSb
CLAVSb
ENS
b
Data c 0
Vcc
Data c 1
Data c 2
Data c 3
Data c 4
Data c 5
GND
Data c 6
Data c 7
Data c 8
SOCSc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
77301
100 PIN
TQFP
PN-100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
GND
BSS
ADR0
ADR1
ADR2
ADR3
ADR4
WCLK
DATA 0
Vcc
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9/P_ID0
GND
Data 10/P_ID1
Data 11/P_CS0
Data 12/P_CS1
Data 13/P_CS2
RST
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
2
CLAVR
GND
SOCR
Data17/P_CS6
Data16/P_CS5
Data15/P_CS4
Data14/P_CS3
CLAVSc
Vcc
ENS
c
Data d 0
Data d 1
Data d 2
Data d 3
GND
Data d 4
Data d 5
Data d 6
Data d 7
Data d 8
Vcc
SOCSd
CLAVSd
ENS
d
ENR
3 2 4 0 d rw 0 2
IDT77301
UtopiaFIFO™ 1 to 4 (128 x 9 x 4) Demultiplexer-FIFO
Commercial and Industrial Temperature Ranges
Pin Description
Symbol
1-2, 4-8,
10, 100
Name
DATA-b
I/O
O
Description
Data bus output for FIFO-b. Master Mode with BNE HIGH: output is a 9-bit word. Master Mode with
BNE LOW: data bus output is a data nibble (Q0-Q3); Q4-Q6 data lines unused; data out Q7 is an
output enable control signal to the slave device; Q8 is an output of bit 9/18 valid during the low and
high nibble transfer. Slave Mode with BNE LOW: data bus output is a data nibble (Q0-Q3); Q4-Q7
lines unused; Q8 is an output of D8/D17 valid during the low and high nibble transfer.
Start Of Cell (FIFO-b). Output from UtopiaFIFO. Active on first byte of data transfer. SOCS deasserts
for all remaining byte transfers.
Cell Available (FIFO-b). CLAVS notifies the UtopiaFIFO port a cell transfer can be initiated by the port.
Enable (FIFO-b). Master Mode:
ENS
is an active low output. When asserted, a data transfer will take
place on the current clock cycle. Slave Mode:
ENS
is an input which causes the fifo port to update a
data nibble (Q0-3) on the output bus on the next read clock edge.
Data bus output for FIFO-c. Master Mode with BNE HIGH: output is a 9-bit word. Master Mode with
BNE LOW: data bus output is a data nibble (Q0-Q-3); Q4-Q6 data lines unused; data out Q7 is an
output enable control signal to the slave device; Q8 is an output of bit 9/18 valid during the low and
high nibble transfer. Slave Mode with BNE LOW: data bus output is a data nibble (Q1-Q3); Q4-Q7
lines unused; Q8 is an output of D8/D17 valid during the low and high nibble transfer.
Start Of Cell (FIFO-c). Output from UtopiaFIFO. Active on first byte of data transfer. SOCS deasserts
for all remaining byte transfers.
Cell Available (FIFO-c) CLAVS notifies the UtopiaFIFO port a cell transfer can be initiated by the port.
Enable (FIFO-c). Master Mode:
ENS
is an active low output. When asserted, a data transfer will take
place on the current clock cycle. Slave Mode:
ENS
is an input which causes the fifo port to update a
data nibble (Q0-3) on the output bus on the next read clock edge.
Data bus output for FIFO-d. Master Mode with BNE HIGH: output is a 9-bit word. Master Mode with
BNE LOW: data bus output is a data nibble (Q0-Q3); Q4-Q6 data lines unused; data out Q7 is an
output enable control signal to the slave device; Q8 is an output of bit 9/18 valid during the low and
high nibble transfer. Slave Mode with BNE LOW; data bus output is a data nibble (Q0-Q3); Q4-Q7
lines unused; Q8 is an output of D8/D17 valid during the low and high nibble transfer.
Start Of Cell (FIFO-d). Output from UtopiaFIFO. Active on first byte of data transfer. SOCS deasserts
for all remaining byte transfers.
Cell Available (FIFO-d). CLAVS notifies the UtopiaFIFO port a cell transfer can be initiated by the port.
Enable (FIFO-d). Master Mode:
ENS
is an active low output. When asserted, a data transfer will take
place on the current clock cycle. Slave Mode:
ENS
is an input which causes the fifo port to update a
data nibble (Q0-3) on the output bus on the next read clock edge.
Input port write enable. Each data write requires
ENR
assertion.
Input port Cell space Available. Notifies the controlling agent the FIFO(s) selected by the address
bus can accept a complete cell.
Input port Start of Cell. Assertion: first work is currently on bus.
BSS low (18-Bit bus): Data bus input Data 11-Data 17
BSS high (9-bit bus): Input port for loading programmable registers.
3240 tbl 01
11
12
13
SOCS-b
CLAVS-b
O
I
I/O
ENS
-b
14, 16-20,
22-24
DATA-c
O
25
26
28
SOCS-c
CLAVS-c
O
I
I/O
ENS
-c
29-32,
34-38
DATA-d
O
40
41
42
SOCS-d
CLAVS-d
O
I
I/O
ENS
-d
43
44
46
47-53
ENR
CLAVR
SOCR
Data 17-11/
P_CS 6-0
I
O
I
I
3
IDT77301
UtopiaFIFO™ 1 to 4 (128 x 9 x 4) Demultiplexer-FIFO
Commercial and Industrial Temperature Ranges
Pin Description
Symbol
54, 56
57-64, 66
68
69-73
Name
Data 9-10 /
P_ID 0-1
Data 0-8
I/O
I
I
I
I
Description
18-Bit bus: Data bus input
9-bit bus: Parallel programmable register load (ID0, ID1)
Data bus input
Reset. Clears all FIFO memory locations, cell size read/write pointers.
Address Location(s). Provide cell destination and multicast addresses. Singlecast Operation: for out-
band routing, address location is loaded from incoming Utopia Level 2 compliant address lines; for
in-band routing, address location is derived from data lines D0-D17 (see Table 1a). Multicast
Operation for out-band routing, the ADR0-3 signals (ADR4 is not used) act as enables which select
the desired output FIFO combination (see Table 1b); for in-band routing, the output FIFO
co mbindation is derived from the data lines D0-D17.
Bus Size Select. BSS HIGH, the input bus is set to 9-bits (D0-D8) and D9-D17 determine cell size
and chip ID. BSS LOW, the input bus is 18-bits.
Input port Data write clock.
Byte Nibble Enable. BNE HIGH, output ports are byte wide data buses. BNE LOW, output data is in
4-bit "nibble" increments using Q0-Q3. This mode supports wide input data bus applications of 32 to
72-bit widths.
Multicast/Address Select. Determines single or multicast input mode. Selecting MAS HIGH sets the
device to multicast mode with ADR0-3 as enables. MAS LOW the device is set to single destination
mode with ADR0-4 lines as address lines.
Routing Method Select. With RMS HIGH, In-band Routing is selected. With RMS LOW, Out-band
Routing is selected.
Master Slave Enable. With MSE set HIGH, device is set as a master; with MSE LOW, device is set
as a slave.
Serial Load Enable.
Serial Load Clock.
BSS low, Serial data load. BSS high Serial input port for loading programmable registers.
Output Enable. Tri-States all data output buses.
Data read clock.
Data bus output for FIFO-a. Master Mode with BNE HIGH: output is a 9-bit word. Master Mode with
BNE LOW: data bus output is a data nibble (Q0-Q3); Q4-Q6 data lines unused; data out Q7 is an
output enable control signal to the slave device; Q8 is an output of bit 9/18 valid during the low and
high nibble transfer. Slave Mode with BNE LOW: data bus output is a data nibble (Q0-Q3); Q4-Q7
lines unused; Q8 is an output of D8/D17 valid during the low and high nibble transfer.
Start Of Cell (FIFO-a) output from UtopiaFIFO. Active on first byte of data transfer. SOCS deasserts for
all remaining byte transfers.
Cell Available (FIFO-a). CLAVS notifies the UtopiaFIFO port. A cell transfer can be initiated by
the port.
Enable (FIFO-a). Master Mode:
ENS
is an active low output. When asserted, a data transfer will take
place on the current clock cycle. Slave Mode:
ENS
is an input which causes the fifo port to update a
data nibble (Q0-3) on the output bus on the next read clock edge.
Lo gic and supply ground pins 9, 21, 33, 45, 55, 75, 85 and 97.
Logic and supply V
CC
pins 3, 15, 27, 39, 65, and 91.
3240 tbl 02
RST
ADR0-4
74
67
76
BSS
WCLK
BNE
I
I
I
77
MAS
I
78
79
80
81
82
83
84
86-90,
92-95
RMS
MSE
I
I
I
I
I
I
I
O
SLE
SCLK
SDI/P_ID0
OE
RCLK
DATA-a
96
98
99
SOCS-1
CLAVS-a
O
I
I/O
ENS
-s
GND
V
CC
____
____
4
IDT77301
UtopiaFIFO™ 1 to 4 (128 x 9 x 4) Demultiplexer-FIFO
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings
Symbol
V
TERM
T
A
T-Bias
T-STG
I
OUT
Terminal Voltage with respect to ground
Operating Temperature
Temperature under Bias
Storage Temperature
DC Output Current
Rating
Commercial
-0.5 to +7.0
0 to +70
-55 to +155
-55 to +155
50
Industrial
-0.5 to +7.0
-40 to +85
-55 to +155
-55 to +155
50
Unit
V
C
C
C
mA
3240 tbl 03
Recommended DC Operating Conditions
Symbol
V
CC
GND
V
IH
V
IL
Commercial Supply Voltage
Supply Voltage
Input High Voltage Commercial
Input Low Voltage Commercial
Parameter
Min.
4.5
0
2.0
-0.3
Typ.
5.0
0
____
____
Max.
5.5
0
V
CC
+0.3
0.8
Unit
V
V
V
V
3240 tbl 04
DC Electrical Characteristics
Symbol
I
LI
I
LO
V
OH
V
OL
I
CC1
Input Leakage Current
Output Leakage Current
Output Logic "1" Voltage, I
OH
=-4mA@2.4V
Output Logic "0" Voltage I
OL
=+4mA@0.4V
Input Low Voltage Commercial
Parameter
Min.
-1
-10
2.4
____
Typ.
____
Max.
1
10
____
Unit
µA
µA
V
V
mA
3240 tbl 05
____
____
____
0.4
150
____
____
Capacitance
Symbol
C
IN
C
OUT
Input Capacitance
Output Capacitance
Parameter
Conditions
V
IN
=0V
V
OUT
=0V
Max.
10
10
Unit
pF
pF
3240 tbl 06
Current
Symbol
I
CC
-Active
I
CC
-DC
Active Power Supply Current @ 20 MHz
DC Power Supply
Parameter
Conditions
Max.
45
30
Unit
mA
mA
3240 tbl 07
OE
= High
OE
= High
5
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