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CAT5401BI-50-TE13

产品描述Quad Digitally Programmable Potentiometers (DPP⑩) with 64 Taps and SPI Interface
产品类别模拟混合信号IC    转换器   
文件大小98KB,共17页
制造商Catalyst
官网地址http://www.catalyst-semiconductor.com/
下载文档 详细参数 全文预览

CAT5401BI-50-TE13概述

Quad Digitally Programmable Potentiometers (DPP⑩) with 64 Taps and SPI Interface

CAT5401BI-50-TE13规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称Catalyst
零件包装代码BGA
包装说明VFBGA, BGA24,4X6,20
针数24
Reach Compliance Codeunknow
ECCN代码EAR99
其他特性NONVOLATILE MEMORY
控制接口3-WIRE SERIAL
转换器类型DIGITAL POTENTIOMETER
JESD-30 代码R-PBGA-B24
JESD-609代码e0
功能数量4
位置数64
端子数量24
最高工作温度85 °C
最低工作温度-40 °C
封装主体材料PLASTIC/EPOXY
封装代码VFBGA
封装等效代码BGA24,4X6,20
封装形状RECTANGULAR
封装形式GRID ARRAY, VERY THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度)240
电源3/5 V
认证状态Not Qualified
电阻定律LINEAR
最大电阻容差20%
最大电阻器端电压3 V
最小电阻器端电压
座面最大高度0.765 mm
标称供电电压3 V
表面贴装YES
技术CMOS
标称温度系数300 ppm/°C
温度等级INDUSTRIAL
端子面层TIN LEAD
端子形式BALL
端子节距0.5 mm
端子位置BOTTOM
处于峰值回流温度下的最长时间30
标称总电阻50000 Ω

文档预览

下载PDF文档
CAT5401
Quad Digitally Programmable Potentiometers (DPP™)
with 64 Taps and SPI Interface
FEATURES
s
Four linear-taper digitally programmable
H
GEN
FR
ALO
EE
LE
A
D
F
R
E
E
TM
s
Automatic recall of saved wiper settings at
potentiometers
s
64 resistor taps per potentiometer
s
End to end resistance 2.5k
, 10k
, 50k
or 100k
s
Potentiometer control and memory access via
power up
s
2.5 to 6.0 volt operation
s
Standby current less than 1
µ
A
s
1,000,000 nonvolatile WRITE cycles
s
100 year nonvolatile memory data retention
s
24-lead SOIC, 24-lead TSSOP and BGA
s
Industrial temperature range
SPI interface: Mode (0, 0) and (1, 1)
s
Low wiper resistance, typically 80Ω
s
Nonvolatile memory storage for up to four wiper
settings for each potentiometer
DESCRIPTION
The CAT5401 is four Digitally Programmable
Potentiometers (DPPs™) integrated with control logic
and 16 bytes of NVRAM memory. Each DPP consists of
a series of 63 resistive elements connected between two
externally accessible end points. The tap points between
each resistive element are connected to the wiper outputs
with CMOS switches. A separate 6-bit control register
(WCR) independently controls the wiper tap switches for
each DPP. Associated with each wiper control register
are four 6-bit non-volatile memory data registers (DR)
used for storing up to four wiper settings. Writing to the
wiper control register or any of the non-volatile data
registers is via a SPI serial bus. On power-up, the
contents of the first data register (DR0) for each of the
four potentiometers is automatically loaded into its
respective wiper control register.
The CAT5401 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
PIN CONFIGURATION
SOIC Package (J, W)
VCC
RL0
RH0
RW0
CS
WP
SI
A1
RL1
RH1
RW1
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
CAT
19
5401
18
17
16
15
14
13
1
A
B
RW0
RL0
VCC
NC
RL3
RW3
NC
RL3
RH3
RW3
A0
SO
HOLD
SCK
RL2
RH2
RW2
NC
2
CS
WP
RH0
RH3
SO
A0
SI
A1
RL1
RH1
RW1
GND
NC
RW2
RH2
RL2
SCK
HOLD
3
A1
SI
RH1
RH2
HOLD
SCK
TSSOP Package (U, Y)
1
2
3
4
5
6
7
8
9
10
11
12
4
RL1
RW1
VSS
NC
RW2
RL2
24
23
22
21
20
CAT
19
5401
18
17
16
15
14
13
WP
CS
RW0
RH0
RL0
VCC
NC
RL3
RH3
RW3
A0
SO
FUNCTIONAL DIAGRAM
RH0 RH1
RH2 R H3
CS
SCK
SI
SO
SPI BUS
INTERFACE
WIPER
CONTROL
REGISTERS
R W0
R W1
R W2
WP
A0
A1
CONTROL
LOGIC
NONVOLATILE
DATA
REGISTERS
R W3
RL0 RL1
RL2 R L3
BGA
C
D
E
F
Top View - Bump Side Down
Document No. 2010, Rev. F
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
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