Philips Semiconductors
Product specification
Triacs
logic level
GENERAL DESCRIPTION
Glass passivated, sensitive gate triacs
in a plastic envelope suitable for
surface mounting, intended for use in
general
purpose
bidirectional
switching
and
phase
control
applications. These devices are
intended to be interfaced directly to
microcontrollers, logic integrated
circuits and other low power gate
trigger circuits.
BT134W series D
QUICK REFERENCE DATA
SYMBOL
V
DRM
I
T(RMS)
I
TSM
PARAMETER
BT134W-
Repetitive peak off-state voltages
RMS on-state current
Non-repetitive peak on-state current
MAX. MAX. UNIT
500D
500
1
10
600D
600
1
10
V
A
A
PINNING - SOT223
PIN
1
2
3
tab
DESCRIPTION
main terminal 1
PIN CONFIGURATION
4
SYMBOL
T2
main terminal 2
gate
main terminal 2
1
2
3
T1
G
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134).
SYMBOL
V
DRM
I
T(RMS)
I
TSM
PARAMETER
Repetitive peak off-state
voltages
RMS on-state current
Non-repetitive peak
on-state current
I
2
t for fusing
Repetitive rate of rise of
on-state current after
triggering
full sine wave; T
sp
≤
108 ˚C
full sine wave; T
j
= 25 ˚C prior to
surge
t = 20 ms
t = 16.7 ms
t = 10 ms
I
TM
= 1.5 A; I
G
= 0.2 A;
dI
G
/dt = 0.2 A/µs
T2+ G+
T2+ G-
T2- G-
T2- G+
CONDITIONS
MIN.
-
-
-
-
-
-
-
-
-
-
-
-
-
-40
-
-500
500
1
1
10
11
0.5
50
50
50
10
2
5
5
0.5
150
125
MAX.
-600
600
1
UNIT
V
A
A
A
A
2
s
A/µs
A/µs
A/µs
A/µs
A
V
W
W
˚C
˚C
I
2
t
dI
T
/dt
I
GM
V
GM
P
GM
P
G(AV)
T
stg
T
j
Peak gate current
Peak gate voltage
Peak gate power
Average gate power
Storage temperature
Operating junction
temperature
over any 20 ms period
1
Although not recommended, off-state voltages up to 800V may be applied without damage, but the triac may
switch to the on-state. The rate of rise of current should not exceed 3 A/µs.
August 1997
1
Rev 1.200
Philips Semiconductors
Product specification
Triacs
logic level
THERMAL RESISTANCES
SYMBOL
R
th j-sp
R
th j-a
PARAMETER
Thermal resistance
junction to solder point
Thermal resistance
junction to ambient
CONDITIONS
full or half cycle
pcb mounted; minimum footprint
pcb mounted; pad area as in fig:14
MIN.
-
-
-
BT134W series D
TYP.
-
156
70
MAX.
15
-
-
UNIT
K/W
K/W
K/W
STATIC CHARACTERISTICS
T
j
= 25 ˚C unless otherwise stated
SYMBOL
I
GT
PARAMETER
Gate trigger current
CONDITIONS
V
D
= 12 V; I
T
= 0.1 A
T2+ G+
T2+ G-
T2- G-
T2- G+
T2+ G+
T2+ G-
T2- G-
T2- G+
MIN.
-
-
-
-
-
-
-
-
-
-
-
0.25
-
TYP.
2.0
2.5
2.5
5.0
1.6
4.5
1.2
2.2
1.2
1.2
0.7
0.4
0.1
MAX.
5
5
5
10
10
15
10
15
10
1.5
1.5
-
0.5
UNIT
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
V
V
mA
I
L
Latching current
V
D
= 12 V; I
GT
= 0.1 A
I
H
V
T
V
GT
I
D
Holding current
On-state voltage
Gate trigger voltage
Off-state leakage current
V
D
= 12 V; I
GT
= 0.1 A
I
T
= 2 A
V
D
= 12 V; I
T
= 0.1 A
V
D
= 400 V; I
T
= 0.1 A; T
j
= 125 ˚C
V
D
= V
DRM(max)
; T
j
= 125 ˚C
DYNAMIC CHARACTERISTICS
T
j
= 25 ˚C unless otherwise stated
SYMBOL
dV
D
/dt
t
gt
PARAMETER
Critical rate of change of
off-state voltage
Gate controlled turn-on
time
CONDITIONS
V
DM
= 67% V
DRM(max)
; T
j
= 125 ˚C;
exponential waveform; R
GK
= 1 kΩ
I
TM
= 1.5 A; V
D
= V
DRM(max)
; I
G
= 0.1 A;
dI
G
/dt = 5 A/µs
MIN.
-
-
TYP.
5
2
MAX.
-
-
UNIT
V/µs
µs
August 1997
2
Rev 1.200
Philips Semiconductors
Product specification
Triacs
logic level
BT134W series D
1.4
1.2
Ptot / W
BT134W
Tsp(max) / C
104
107
1.2
1
0.8
IT(RMS) / A
BT134W
108 C
= 180
1
1
0.8
0.6
0.4
0.2
0
120
90
60
30
110
113
0.6
116
119
122
125
1.2
0.4
0.2
0
-50
0
0.2
0.4
0.6
0.8
IT(RMS) / A
1
0
50
Tsp / C
100
150
Fig.1. Maximum on-state dissipation, P
tot
, versus rms
on-state current, I
T(RMS)
, where
α
= conduction angle.
BT134W
IT
T
100
dI
T
/dt limit
I TSM
time
Fig.4. Maximum permissible rms current I
T(RMS)
,
versus solder point temperature T
sp
.
IT(RMS) / A
BT134W
1000
ITSM / A
2
1.5
Tj initial = 25 C max
1
T2- G+ quadrant
10
0.5
1
10us
100us
1ms
T/s
10ms
100ms
0
0.01
0.1
surge duration / s
1
10
Fig.2. Maximum permissible non-repetitive peak
on-state current I
TSM
, versus pulse width t
p
, for
sinusoidal currents, t
p
≤
20ms.
BT134W
IT
T
8
6
4
2
0
ITSM
time
Fig.5. Maximum permissible repetitive rms on-state
current I
T(RMS)
, versus surge duration, for sinusoidal
currents, f = 50 Hz; T
sp
≤
108˚C.
VGT(Tj)
VGT(25 C)
12
10
ITSM / A
1.6
1.4
1.2
1
0.8
0.6
BT136
Tj initial = 25 C max
1
10
100
Number of cycles at 50Hz
1000
0.4
-50
0
50
Tj / C
100
150
Fig.3. Maximum permissible non-repetitive peak
on-state current I
TSM
, versus number of cycles, for
sinusoidal currents, f = 50 Hz.
Fig.6. Normalised gate trigger voltage
V
GT
(T
j
)/ V
GT
(25˚C), versus junction temperature T
j
.
August 1997
3
Rev 1.200
Philips Semiconductors
Product specification
Triacs
logic level
BT134W series D
3
2.5
2
1.5
1
0.5
IGT(Tj)
IGT(25 C)
BT136D
T2+ G+
T2+ G-
T2- G-
T2- G+
2
IT / A
Tj = 125 C
Tj = 25 C
BT134W
1.5
Vo = 1.0 V
Rs = 0.21 Ohms
typ
1
max
0.5
0
-50
0
0
50
Tj / C
100
150
0
0.5
1
VT / V
1.5
2
Fig.7. Normalised gate trigger current
I
GT
(T
j
)/ I
GT
(25˚C), versus junction temperature T
j
.
IL(Tj)
IL(25 C)
Fig.10. Typical and maximum on-state characteristic.
3
2.5
2
1.5
1
0.5
TRIAC
100
Zth j-sp (K/W)
BT134W
10
unidirectional
1
bidirectional
P
D
tp
0.1
t
0
-50
0
50
Tj / C
100
150
0.01
10us
0.1ms
1ms
10ms
tp / s
0.1s
1s
10s
Fig.8. Normalised latching current I
L
(T
j
)/ I
L
(25˚C),
versus junction temperature T
j
.
IH(Tj)
IH(25C)
Fig.11. Transient thermal impedance Z
th j-sp
, versus
pulse width t
p
.
dVD/dt (V/us)
3
2.5
2
1.5
1
0.5
TRIAC
1000
100
10
0
-50
0
50
Tj / C
100
150
1
0
50
Tj / C
100
150
Fig.9. Normalised holding current I
H
(T
j
)/ I
H
(25˚C),
versus junction temperature T
j
.
Fig.12. Typical, critical rate of rise of off-state voltage,
dV
D
/dt versus junction temperature T
j
.
August 1997
4
Rev 1.200
Philips Semiconductors
Product specification
Triacs
logic level
MOUNTING INSTRUCTIONS
BT134W series D
Dimensions in mm.
3.8
min
1.5
min
2.3
1.5
min
(3x)
6.3
1.5
min
4.6
Fig.13. soldering pattern for surface mounting SOT223.
PRINTED CIRCUIT BOARD
Dimensions in mm.
36
18
60
9
4.6
4.5
10
7
15
50
Fig.14. PCB for thermal resistance and power rating for SOT223.
PCB: FR4 epoxy glass (1.6 mm thick), copper laminate (35
µ
m thick).
August 1997
5
Rev 1.200
FPGA/CPLD
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