LTC2220-1
12-Bit,185Msps ADC
FEATURES
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DESCRIPTIO
■
Sample Rate: 185Msps
67.5dB SNR up to 140MHz Input
80dB SFDR up to 170MHz Input
775MHz Full Power Bandwidth S/H
Single 3.3V Supply
Low Power Dissipation: 910mW
LVDS, CMOS, or Demultiplexed CMOS Outputs
Selectable Input Ranges:
±0.5V
or
±1V
No Missing Codes
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Data Ready Output Clock
Pin Compatible Family
185Msps: LTC2220-1 (12-Bit)
170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit)
135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit)
64-Pin 9mm
×
9mm QFN Package
The LTC
®
2220-1 is a 185Msps, sampling 12-bit A/D
converter designed for digitizing high frequency, wide
dynamic range signals. The LTC2220-1 is perfect for
demanding communications applications with AC perfor-
mance that includes 67.5dB SNR and 80dB spurious free
dynamic range for signals up to 170MHz. Ultralow jitter of
0.15ps
RMS
allows undersampling of IF frequencies with
excellent noise performance.
DC specs include
±0.7LSB
INL (typ),
±0.5LSB
DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.5LSB
RMS
.
The digital outputs can be either differential LVDS, or
single-ended CMOS. There are three format options for
the CMOS outputs: a single bus running at the full data rate
or two demultiplexed buses running at half data rate with
either interleaved or simultaneous update. A separate
output power supply allows the CMOS output swing to
range from 0.5V to 3.6V.
The ENC
+
and ENC
–
inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL, or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
APPLICATIO S
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Wireless and Wired Broadband Communication
Cable Head-End Systems
Power Amplifier Linearization
Communications Test Equipment
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATIO
3.3V
REFH
REFL
FLEXIBLE
REFERENCE
V
DD
0.5V
TO 3.6V
OV
DD
100
90
4th OR HIGHER
SFDR (dBFS)
+
ANALOG
INPUT
INPUT
S/H
–
12-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
OUTPUT
DRIVERS
D11
•
•
•
D0
80
70
2nd OR 3rd
60
50
40
CMOS
OR
LVDS
OGND
CLOCK/DUTY
CYCLE
CONTROL
22201 TA01
ENCODE
INPUT
U
SFDR vs Input Frequency
0
100
400
500
600
INPUT FREQUENCY (MHz)
22201 TA01b
2220_1fa
U
U
200
300
1
LTC2220-1
ABSOLUTE
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW
OV
DD
= V
DD
(Notes 1, 2)
Supply Voltage (V
DD
) ................................................. 4V
Digital Output Ground Voltage (OGND) ....... –0.3V to 1V
Analog Input Voltage (Note 3) ..... –0.3V to (V
DD
+ 0.3V)
Digital Input Voltage .................... –0.3V to (V
DD
+ 0.3V)
Digital Output Voltage ............... –0.3V to (OV
DD
+ 0.3V)
Power Dissipation ............................................ 1500mW
Operating Temperature Range
LTC2220-1C ............................................ 0°C to 70°C
LTC2220-1I .........................................–40°C to 85°C
Storage Temperature Range ..................–65°C to 125°C
A
IN+
1
A
IN+
2
A
IN–
3
A
IN–
4
REFHA 5
REFHA 6
REFLB 7
REFLB 8
REFHB 9
REFHB 10
REFLA 11
REFLA 12
V
DD
13
V
DD
14
V
DD
15
GND 16
64 GND
63 V
DD
62 V
DD
61 GND
60 V
CM
59 SENSE
58 MODE
57 LVDS
56 OF
+
/OFA
55 OF
–
/DA11
54 D11
+
/DA10
53 D11
–
/DA9
52 D10
+
/DA8
51 D10
–
/DA7
50 OGND
49 OV
DD
65
48 D9
+
/DA6
47 D9
–
/DA5
46 D8
+
/DA4
45 D8
–
/DA3
44 D7
+
/DA2
43 D7
–
/DA1
42 OV
DD
41 OGND
40 D6
+
/DA0
39 D6
–
/CLOCKOUTA
38 D5
+
/CLOCKOUTB
37 D5
–
/OFB
36 CLOCKOUT
+
/DB11
35 CLOCKOUT
–
/DB10
34 OV
DD
33 OGND
T
JMAX
= 125°C,
θ
JA
= 20°C/W
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
ORDER PART NUMBER
LTC2220CUP-1
LTC2220IUP-1
Order Options
Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking:
http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.
CO VERTER CHARACTERISTICS
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 4)
PARAMETER
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error
Offset Drift
Full-Scale Drift
Transition Noise
Internal Reference
External Reference
SENSE = 1V
Differential Analog Input (Note 5)
Differential Analog Input
Single-Ended Analog Input (Note 5)
Single-Ended Analog Input
(Note 6)
External Reference
●
●
CONDITIONS
●
●
●
ENC
+
17
ENC
–
18
SHDN 19
OE 20
DO
–
/DB0 21
DO
+
/DB1 22
D1
–
/DB2 23
D1
+
/DB3 24
OGND 25
OV
DD
26
D2
–
/DB4 27
D2
+
/DB5 28
D3
–
/DB6 29
D3
+
/DB7 30
D4
–
/DB8 31
D4
+
/DB9 32
UP PACKAGE
64-LEAD (9mm
×
9mm) PLASTIC QFN
UP PART MARKING*
LTC2220UP-1
MIN
12
–1.8
–1
TYP
±0.7
±0.5
±1.5
±0.5
MAX
1.8
1.2
UNITS
Bits
LSB
LSB
LSB
LSB
–35
–2.5
±3
±0.5
±10
±30
±15
0.5
35
2.5
ppm/C
ppm/C
LSB
RMS
2220_1fa
2
U
mV
%FS
µV/C
W
U
U
W W
W
U
LTC2220-1
The
●
denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at T
A
= 25°C. (Note 4)
SYMBOL
V
IN
V
IN, CM
I
IN
I
SENSE
I
MODE
I
LVDS
t
AP
t
JITTER
CMRR
PARAMETER
Analog Input Range (A
IN+
– A
IN–
)
Analog Input Common Mode (A
IN+
+ A
IN–
)/2
Analog Input Leakage Current
SENSE Input Leakage
MODE Pin Pull-Down Current to GND
LVDS Pin Pull-Down Current to GND
Sample and Hold Acquisition Delay Time
Sample and Hold Acquisition Delay Time Jitter
Analog Input Common Mode Rejection Ratio
Full Power Bandwidth
Figure 8 Test Circuit
CONDITIONS
3.1V < V
DD
< 3.5V (Note 7)
Differential Input (Note 7)
Single Ended Input (Note 7)
0 < A
IN+
, A
IN–
< V
DD
0V < SENSE < 1V
●
●
●
●
●
A ALOG I PUT
DY A IC ACCURACY
SYMBOL
SNR
PARAMETER
The
●
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. A
IN
= –1dBFS. (Note 4)
CONDITIONS
5MHz Input (1V Range)
5MHz Input (2V Range)
70MHz Input (1V Range)
70MHz Input (2V Range)
140MHz Input (1V Range)
140MHz Input (2V Range)
250MHz Input (1V Range)
250MHz Input (2V Range)
●
Signal-to-Noise Ratio (Note 10)
SFDR
Spurious Free Dynamic Range
2nd or 3rd Harmonic (Note 11)
SFDR
Spurious Free Dynamic Range
4th Harmonic or Higher (Note 11)
S/(N+D)
Signal-to-Noise Plus
Distortion Ratio (Note 12)
IMD
Intermodulation Distortion
U
W U
U
MIN
1
0.5
–1
–1
TYP
±0.5
to
±1
1.6
1.6
MAX
1.9
2.1
1
1
UNITS
V
V
V
µA
µA
µA
µA
ns
ps
RMS
dB
MHz
10
10
0
0.15
80
775
MIN
TYP
62.7
67.7
MAX
UNITS
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dBc
2220_1fa
65.2
62.7
67.6
62.4
67.5
61.8
66.1
80
80
5MHz Input (1V Range)
5MHz Input (2V Range)
70MHz Input (1V Range)
70MHz Input (2V Range)
140MHz Input (1V Range)
140MHz Input (2V Range)
250MHz Input (1V Range)
250MHz Input (2V Range)
5MHz Input (1V Range)
5MHz Input (2V Range)
70MHz Input (1V Range)
70MHz Input (2V Range)
140MHz Input (1V Range)
140MHz Input (2V Range)
250MHz Input (1V Range)
250MHz Input (2V Range)
5MHz Input (1V Range)
5MHz Input (2V Range)
70MHz Input (1V Range)
70MHz Input (2V Range)
f
IN1
= 138MHz, f
IN2
= 140MHz
●
●
●
69
80
80
80
80
74
73
85
85
74
85
85
84
84
83
83
62.7
67.5
64.2
62.7
67.3
81
3
LTC2220-1
I TER AL REFERE CE CHARACTERISTICS
(Note 4)
PARAMETER
V
CM
Output Voltage
V
CM
Output Tempco
V
CM
Line Regulation
V
CM
Output Resistance
3.1V < V
DD
< 3.5V
–1mA < I
OUT
< 1mA
CONDITIONS
I
OUT
= 0
MIN
1.570
TYP
1.600
±25
3
4
MAX
1.630
UNITS
V
ppm/°C
mV/V
Ω
DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL
V
ID
V
ICM
R
IN
C
IN
V
IH
V
IL
I
IN
C
IN
OV
DD
= 3.3V
C
OZ
I
SOURCE
I
SINK
V
OH
V
OL
OV
DD
= 2.5V
V
OH
V
OL
OV
DD
= 1.8V
V
OH
V
OL
V
OD
V
OS
High Level Output Voltage
Low Level Output Voltage
Differential Output Voltage
Output Common Mode Voltage
I
O
= –200µA
I
O
= 1.6mA
100Ω Differential Load
100Ω Differential Load
High Level Output Voltage
Low Level Output Voltage
I
O
= –200µA
I
O
= 1.6mA
Hi-Z Output Capacitance
Output Source Current
Output Sink Current
High Level Output Voltage
Low Level Output Voltage
OE = High (Note 7)
V
OUT
= 0V
V
OUT
= 3.3V
I
O
= –10µA
I
O
= –200µA
I
O
= 10µA
I
O
= 1.6mA
PARAMETER
Differential Input Voltage
Common Mode Input Voltage
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
Input Current
Input Capacitance
(Note 7)
V
DD
= 3.3V
V
DD
= 3.3V
V
IN
= 0V to V
DD
(Note 7)
Internally Set
Externally Set (Note 7)
CONDITIONS
ENCODE INPUTS (ENC
+
, ENC
–
)
The
●
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T
A
= 25°C. (Note 4)
MIN
●
●
LOGIC INPUTS (OE, SHDN)
●
●
●
LOGIC OUTPUTS (CMOS MODE)
3
50
50
●
●
LOGIC OUTPUTS (LVDS MODE)
●
●
4
U
U
U
U
U
TYP
MAX
UNITS
V
0.2
1.1
1.6
1.6
6
3
2
0.8
–10
3
10
2.5
V
V
kΩ
pF
V
V
µA
pF
pF
mA
mA
V
V
0.4
V
V
V
V
V
V
454
1.375
mV
V
3.1
3.295
3.29
0.005
0.09
2.49
0.09
1.79
0.09
247
1.125
350
1.250
2220_1fa
LTC2220-1
POWER REQUIRE E TS
SYMBOL
V
DD
P
SHDN
P
NAP
LVDS OUTPUT MODE
OV
DD
I
VDD
I
OVDD
P
DISS
OV
DD
I
VDD
P
DISS
Output Supply Voltage
Analog Supply Current
Output Supply Current
Power Dissipation
Output Supply Voltage
Analog Supply Current
Power Dissipation
PARAMETER
Analog Supply Voltage
Shutdown Power
Nap Mode Power
The
●
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 9)
CONDITIONS
(Note 8)
SHDN = High, OE = High, No CLK
SHDN = High, OE = Low, No CLK
(Note 8)
●
●
●
●
●
CMOS OUTPUT MODE
(Note 8)
●
●
TI I G CHARACTERISTICS
SYMBOL
f
S
t
L
t
H
t
AP
t
OE
t
D
t
C
PARAMETER
Sampling Frequency
ENC Low Time (Note 7)
ENC High Time (Note 7)
Sample-and-Hold Aperture Delay
Output Enable Delay
ENC to DATA Delay
ENC to CLOCKOUT Delay
DATA to CLOCKOUT Skew
Rise Time
Fall Time
Pipeline Latency
CMOS OUTPUT MODE
t
D
t
C
Pipeline Latency
ENC to DATA Delay
ENC to CLOCKOUT Delay
DATA to CLOCKOUT Skew
Full Rate CMOS
Demuxed Interleaved
Demuxed Simultaneous
The
●
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 4)
CONDITIONS
(Note 8)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
(Note 7)
(Note 7)
(Note 7)
(t
C
- t
D
) (Note 7)
●
●
●
●
●
●
●
●
●
LVDS OUTPUT MODE
1.3
1.3
–0.6
2.2
2.2
0
0.5
0.5
5
(Note 7)
(Note 7)
(t
C
- t
D
) (Note 7)
●
●
●
U W
MIN
3.1
TYP
3.3
2
35
MAX
3.5
UNITS
V
mW
mW
3
3.3
273
55
1080
3.6
300
70
1221
3.6
300
V
mA
mA
mW
V
mA
mW
0.5
3.3
273
910
UW
MIN
1
2.5
2
2.5
2
TYP
2.7
2.7
2.7
2.7
0
5
MAX
185
500
500
500
500
10
3.5
3.5
0.6
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.3
1.3
–0.6
2.1
2.1
0
5
5
5 and 6
3.5
3.5
0.6
ns
ns
ns
Cycles
Cycles
Cycles
2220_1fa
5
stm32/stm8
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