Datasheet> 器件分类 > 嵌入式处理器和控制器> 微控制器和处理器> CN80617004116AD/SLBPF

文档预览

CN80617004116AD/SLBPF: 产品描述RISC Microprocessor, 64-Bit, 2530MHz, CMOS, PBGA1288; 产品类别嵌入式处理器和控制器微控制器和处理器; 文件大小2MB，共388页; 制造商Intel(英特尔); 官网地址http://www.intel.com/; 标准

下载文档详细参数选型对比全文预览

CN80617004116AD/SLBPF概述

RISC Microprocessor, 64-Bit, 2530MHz, CMOS, PBGA1288

CN80617004116AD/SLBPF规格参数

参数名称	属性值
是否Rohs认证	符合
包装说明	BGA, BGA1288(UNSPEC)
Reach Compliance Code	compli
位大小	64
端子数量	1288
封装主体材料	PLASTIC/EPOXY
封装代码	BGA
封装等效代码	BGA1288(UNSPEC)
封装形式	GRID ARRAY
电源	0.75/1.35 V
认证状态	Not Qualified
速度	2530 MHz
最大压摆率	48000 mA
表面贴装	YES
技术	CMOS
端子形式	BALL
端子位置	BOTTOM
uPs/uCs/外围集成电路类型	MICROPROCESSOR, RISC
Base Number Matches	1

文档预览

下载PDF文档

全文
预览

Intel® Core™ i7-600, i5-500, i5-400

and i3-300 Mobile Processor Series

Datasheet — Volume Two

This is volume 2 of 2. Refer to Document Number 322812 for Volume 1

November 2010

Document Number: 322813-002

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED,

BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS

PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER,

AND INTL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING

LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY

PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or

life sustaining applications.

Legal Lines and Disclaimers

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel

reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future

changes to them.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device

drivers and applications enabled for Intel® 64 architecture. Processors will not operate (including 32-bit operation) without an

Intel® 64 architecture-enabled BIOS. Performance will vary depending on your hardware and software configurations. Consult with

your system vendor for more information

Intel® Core™ i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series may contain design defects or errors known as errata

which may cause the product to deviate from published specifications. Current characterized errata are available on request.



Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor

family, not across different processor families. See

http://www.intel.com/products/processor_number

for details.

Intel, Intel SpeedStep, Itanium and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.

*Other names and brands may be claimed as the property of others.

Datasheet

Contents

Processor Configuration Registers

........................................................................... 12

1.1

1.2

System Address Map.......................................................................................... 14

1.2.1 Legacy Address Range ............................................................................ 17

1.2.2 Main Memory Address Range (1 MB - TOLUD) ............................................ 19

1.2.3 Main Memory Address Space (4 GB to TOUUD) ........................................... 27

1.2.4 PCI Express* Configuration Address Space ................................................ 34

1.2.5 PCI Express Graphics Attach (PEG) ........................................................... 34

1.2.6 Graphics Memory Address Ranges ............................................................ 35

1.2.7 System Management Mode (SMM) ............................................................ 36

1.2.8 SMM and VGA Access through GTT TLB .................................................... 37

1.2.9 I/O Address Space.................................................................................. 37

Configuration Process and Registers..................................................................... 39

1.3.1 Platform Configuration Structure .............................................................. 39

Configuration Mechanisms .................................................................................. 40

1.4.1 Standard PCI Configuration Mechanism ..................................................... 40

1.4.2 PCI Express Enhanced Configuration Mechanism......................................... 40

Routing Configuration Accesses ........................................................................... 42

1.5.1 Internal Device Configuration Accesses...................................................... 43

1.5.2 Bridge Related Configuration Accesses ...................................................... 44

Processor Register Introduction ........................................................................... 45

I/O Mapped Registers ........................................................................................ 46

PCI Device 0 ..................................................................................................... 46

1.8.1 VID - Vendor Identification ...................................................................... 48

1.8.2 DID - Device Identification....................................................................... 48

1.8.3 PCICMD - PCI Command ......................................................................... 49

1.8.4 PCISTS - PCI Status ............................................................................... 51

1.8.5 RID - Revision Identification .................................................................... 52

1.8.6 CC - Class Code ..................................................................................... 53

1.8.7 MLT - Master Latency Timer ..................................................................... 54

1.8.8 HDR - Header Type................................................................................. 54

1.8.9 SVID - Subsystem Vendor Identification .................................................... 54

1.8.10 SID - Subsystem Identification ................................................................. 55

1.8.11 CAPPTR - Capabilities Pointer ................................................................... 55

1.8.12 PXPEPBAR - PCI Express Egress Port Base Address ..................................... 56

1.8.13 MCHBAR - Processor Memory Mapped Register Range Base.......................... 57

1.8.14 GGC - Processor Graphics Control Register................................................. 58

1.8.15 DEVEN - Device Enable ........................................................................... 62

1.8.16 DMIBAR - Root Complex Register Range Base Address ................................ 63

1.8.17 LAC - Legacy Access Control .................................................................... 64

1.8.18 REMAPBASE - Remap Base Address Register .............................................. 66

1.8.19 REMAPLIMIT - Remap Limit Address Register ............................................. 66

1.8.20 TOM - Top of Memory ............................................................................. 67

1.8.21 TOUUD - Top of Upper Usable DRAM ......................................................... 68

1.8.22 GBSM - Graphics Base of Stolen Memory ................................................... 69

1.8.23 BGSM - Base of GTT Stolen Memory.......................................................... 70

1.8.24 TSEGMB - TSEG Memory Base.................................................................. 71

1.8.25 TOLUD - Top of Low Usable DRAM ............................................................ 71

1.3

1.4

1.5

1.6

1.7

1.8

Datasheet

1.9

1.10

1.8.26

1.8.27

1.8.28

1.8.29

1.8.30

1.8.31

1.8.32

1.8.33

Device

1.9.1

1.9.2

1.9.3

1.9.4

1.9.5

1.9.6

1.9.7

1.9.8

1.9.9

1.9.10

1.9.11

1.9.12

1.9.13

1.9.14

1.9.15

1.9.16

1.9.17

1.9.18

1.9.19

1.9.20

1.9.21

1.9.22

1.9.23

1.9.24

1.9.25

1.9.26

1.9.27

1.9.28

1.9.29

1.9.30

1.9.31

1.9.32

1.9.33

1.9.34

1.9.35

1.9.36

Device

1.10.1

1.10.2

1.10.3

1.10.4

1.10.5

1.10.6

1.10.7

PBFC - Primary Buffer Flush Control ..........................................................73

SBFC - Secondary Buffer Flush Control ......................................................73

ERRSTS - Error Status .............................................................................74

ERRCMD - Error Command.......................................................................75

SMICMD - SMI Command.........................................................................76

SCICMD - SCI Command .........................................................................77

SKPD - Scratchpad Data ..........................................................................77

CAPID0 - Capability Identifier ...................................................................78

0 MCHBAR DRAM Controls ........................................................................78

CSZMAP - Channel Size Mapping...............................................................80

CHDECMISC - Channel Decode Misc. .........................................................81

C0DRB0 - Channel 0 DRAM Rank Boundary Address 0 .................................83

C0DRB1 - Channel 0 DRAM Rank Boundary Address 1 .................................84

C0DRB2 - Channel 0 DRAM Rank Boundary Address 2 .................................84

C0DRB3 - Channel 0 DRAM Rank Boundary Address 3 .................................85

C0DRA01 - Channel 0 DRAM Rank 0,1 Attribute ..........................................85

C0DRA23 - Channel 0 DRAM Rank 2,3 Attribute ..........................................87

C0CYCTRKPCHG - Channel 0 CYCTRK PCHG ...............................................88

C0CYCTRKACT - Channel 0 CYCTRK ACT ....................................................89

C0CYCTRKWR - Channel 0 CYCTRK WR......................................................90

C0CYCTRKRD - Channel 0 CYCTRK READ ...................................................91

C0CYCTRKREFR - Channel 0 CYCTRK REFR.................................................92

C0REFRCTRL - Channel 0 DRAM Refresh Control .........................................92

C0CKECTRL - Channel 0 CKE Control .........................................................95

C0ODTCTRL - Channel 0 ODT Control ........................................................96

C0DTC - Channel 0 DRAM Throttling Control...............................................97

C0DTPEW - Channel 0 DRAM Rank Throttling Passive Event..........................98

C0DTAEW - Channel 0 DRAM Rank Throttling Active Event ...........................99

C1DRB0 - Channel 1 DRAM Rank Boundary Address 0 .................................99

C1DRB1 - Channel 1 DRAM Rank Boundary Address 1 ............................... 100

C1DRB2 - Channel 1 DRAM Rank Boundary Address 2 ............................... 100

C1DRB3 - Channel 1 DRAM Rank Boundary Address 3 ............................... 101

C1DRA01 - Channel 1 DRAM Rank 0,1 Attributes....................................... 101

C1DRA23 - Channel 1 DRAM Rank 2,3 Attributes....................................... 102

C1CYCTRKPCHG - Channel 1 CYCTRK PCHG ............................................. 102

C1CYCTRKACT - Channel 1 CYCTRK ACT .................................................. 103

C1CYCTRKWR - Channel 1 CYCTRK WR.................................................... 104

C1CYCTRKRD - Channel 1 CYCTRK READ ................................................. 105

C1CKECTRL - Channel 1 CKE Control ....................................................... 106

C1REFRCTRL - Channel 1 DRAM Refresh Control ....................................... 107

C1ODTCTRL - Channel 1 ODT Control ...................................................... 110

C1DTC - Channel 1 DRAM Throttling Control............................................. 111

C1DTPEW - Channel 1 DRAM Rank Throttling Passive Event........................ 112

C1DTAEW - Channel 1 DRAM Rank Throttling Active Event ......................... 113

DDRMPLL1 - DDR PLL BIOS .................................................................... 114

0 MCHBAR Thermal Management Controls ................................................ 114

TSC1 - Thermal Sensor Control 1 ............................................................ 116

TSS1 - Thermal Sensor Status 1 ............................................................. 117

TR1 - Thermometer Read 1 .................................................................... 118

TOF1 - Thermometer Offset 1................................................................. 119

RTR1 - Relative Thermometer Read 1 ...................................................... 119

TSTTPA1 - Thermal Sensor Temperature Trip Point A1 ............................... 120

TSTTPB1 - Thermal Sensor Temperature Trip Point B1 ............................... 121

Datasheet

1.11

1.12

1.13

1.10.8 HWTHROTCTRL1 - Hardware Throttle Control 1 ........................................ 122

1.10.9 TIS1 - Thermal Interrupt Status 1 .......................................................... 123

1.10.10TERATE - Thermometer Mode Enable and Rate ......................................... 125

1.10.11TERRCMD - Thermal Error Command ...................................................... 127

1.10.12TSMICMD - Thermal SMI Command ........................................................ 128

1.10.13TSCICMD - Thermal SCI Command ......................................................... 129

1.10.14TINTRCMD - Thermal INTR Command ..................................................... 130

1.10.15EXTTSCS - External Thermal Sensor Control and Status............................. 131

1.10.16MCHTSWDT - Memory Controller Thermal Sensor Watch Dog Timer ............ 133

1.10.17MEMTDPCTW - Memory TDP Controller Registers ...................................... 133

1.10.18MTDPCCRWTWHOTTH - Memory TDP Controller Combined RD/WR Thermal

Weight Hot Thresholds .......................................................................... 134

1.10.19MTDPCCRWTWHOTTH2 - Memory TDP Controller Combined RD/WR Thermal

Weight Hot Thresholds 2 ....................................................................... 136

1.10.20MTDPCCRWTWHOTTH3 - Memory TDP Controller Combined RD/WR Thermal

Weight Hot Thresholds 3 ....................................................................... 137

1.10.21MTDPCCRWTWHOTTH4 - Memory TDP Controller Combined RD/WR Thermal

Weight Hot Thresholds 4 ....................................................................... 138

1.10.22MTDPCHOTTHINT - Memory TDP Controller Hot Throttled Intervals ............. 139

1.10.23MTDPCHOTTHINT2 - Memory TDP Controller Hot Throttled Intervals 2 ......... 140

1.10.24MTDPCTLAUXTNTINT - Memory TDP Controller Aux and Throttle-NonThrottle

Intervals ............................................................................................. 141

1.10.25MTDPCMISC - Memory TDP Controller Miscellaneous Control ...................... 141

1.10.26TSFUSE - Thermal Sensor Fuses ............................................................. 142

MCHBAR Render Thermal Throttling Controls....................................................... 143

1.11.1 THERMSTCTL – Render Thermal State Control .......................................... 143

1.11.2 RSTDBYCTL - Render Standby State Control ............................................ 144

1.11.3 VIDCTL - VID Control ............................................................................ 145

1.11.4 WDTMRTS - Watchdog Timer For Thermal Sensor Trip ............................... 145

1.11.5 WDTSTPSZ - Watchdog Timer Based Px Step Size..................................... 145

Device 0 MCHBAR ACPI Power Management Controls ........................................... 146

1.12.1 C3C6ET - C3/C6 EntryTimers ................................................................. 146

1.12.2 SLFRCS - Self-Refresh Channel Status..................................................... 147

1.12.3 DSLFRC - PM Memory Subsystem ........................................................... 147

1.12.4 PMCFG - Power Management Configuration ............................................. 148

PCI Device1.................................................................................................... 148

1.13.1 VID1 - Vendor Identification .................................................................. 151

1.13.2 DID1 - Device Identification ................................................................... 151

1.13.3 PCICMD1 - PCI Command...................................................................... 152

1.13.4 PCISTS1 - PCI Status............................................................................ 154

1.13.5 RID1 - Revision Identification................................................................. 156

1.13.6 CC1 - Class Code.................................................................................. 157

1.13.7 CL1 - Cache Line Size ........................................................................... 157

1.13.8 HDR1 - Header Type ............................................................................. 158

1.13.9 PBUSN1 - Primary Bus Number .............................................................. 158

1.13.10SBUSN1 - Secondary Bus Number .......................................................... 159

1.13.11SUBUSN1 - Subordinate Bus Number ...................................................... 159

1.13.12IOBASE1 - I/O Base Address.................................................................. 160

1.13.13IOLIMIT1 - I/O Limit Address ................................................................. 160

1.13.14SSTS1 - Secondary Status ..................................................................... 161

1.13.15MBASE1 - Memory Base Address ............................................................ 162

1.13.16MLIMIT1 - Memory Limit Address............................................................ 162

1.13.17PMBASE1 - Prefetchable Memory Base Address ........................................ 163

Datasheet

CN80617004116AD/SLBPF相似产品对比

	CN80617004116AD/SLBPF	CP80617004116AD/SLBPG	R35I-200/4-8MM-LD/PP-5/0-7-A-C	CN80617005352AA/SLBQP	CP80617005487AD/SLC28	CP80617003981AH/SLBPD	CN80617006042AB/SLBUG	CP80617004116AH/SLBZX
描述	RISC Microprocessor, 64-Bit, 2530MHz, CMOS, PBGA1288	RISC Microprocessor, 64-Bit, 2530MHz, CMOS, PPGA988	Rotary Position Encoder, Single,	RISC Microprocessor, 64-Bit, 1060MHz, CMOS, PBGA1288	RISC Microprocessor, 64-Bit, 2660MHz, CMOS, PPGA988	RISC Microprocessor, 64-Bit, 2660MHz, CMOS, PPGA988	RISC Microprocessor, 64-Bit, 1200MHz, CMOS, PBGA1288	RISC Microprocessor, 64-Bit, 2530MHz, CMOS, PPGA988
是否Rohs认证	符合	符合	符合	符合	符合	符合	符合	符合
Reach Compliance Code	compli	compli	unknown	compliant	unknown	compliant	compliant	compliant
表面贴装	YES	NO	NO	YES	NO	NO	YES	NO
位大小	64	64	-	64	64	64	64	64
端子数量	1288	988	-	1288	988	988	1288	988
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	BGA	PGA	-	BGA	PGA	PGA	BGA	PGA
封装等效代码	BGA1288(UNSPEC)	PGA988,35X36,40	-	BGA1288(UNSPEC)	PGA988,35X36,40	PGA988,35X36,40	BGA1288(UNSPEC)	PGA988,35X36,40
封装形式	GRID ARRAY	GRID ARRAY	-	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
电源	0.75/1.35 V	0.75/1.35 V	-	0.75/1.35 V	0.75/1.35 V	0.75/1.35 V	0.75/1.35 V	0.75/1.35 V
认证状态	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
速度	2530 MHz	2530 MHz	-	1060 MHz	2660 MHz	2660 MHz	1200 MHz	2530 MHz
最大压摆率	48000 mA	48000 mA	-	48000 mA	48000 mA	48000 mA	48000 mA	48000 mA
技术	CMOS	CMOS	-	CMOS	CMOS	CMOS	CMOS	CMOS
端子形式	BALL	PIN/PEG	-	BALL	PIN/PEG	PIN/PEG	BALL	PIN/PEG
端子位置	BOTTOM	PERPENDICULAR	-	BOTTOM	PERPENDICULAR	PERPENDICULAR	BOTTOM	PERPENDICULAR
uPs/uCs/外围集成电路类型	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	-	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC
Base Number Matches	1	1	-	1	1	1	-	-

推荐资源

今日10点开播：TI Simplelink 平台新一代无线产品解决方案（看点满格哇）: {:1_123:}今日直播推荐看点：彻底告别石英时代、实时测量也能低功耗、多频段。直播时间：今日上午10：00-11：30 直播看点介绍了TI SimpleLink无线平台及各种无线连接技术，着重强调了Sim ......; EEWORLD社区无线连接

在NB-IOT LWM2M 协议设备端的开发中，有没有好的库方便处理AT指令发送和接收的信息: 在NB-IOT LWM2M 协议设备端的开发中，有没有好的现成的库方便处理AT指令发送和接收的信息 ...; 一沙一世单片机

基于CF接口技术的诱发电位测试系统的研究.pdf: 基于CF接口技术的诱发电位测试系统的研究.pdf47318...; yuandayuan6999 单片机

MSP430F5438输出驱动能力寄存器 PxDS: 大家好！最近看MSP430F5438A资料中的输出驱动能力寄存器 PxDS PxDS寄存器中的每一位选择全力驱动或者减弱驱动能力。默认的是减弱驱动能力。 ·位为零：减弱驱动能力 ·位为一：全力驱动能 ......; liuchunhui001 微控制器 MCU

通过童谣和童话故事学习 Python: 本帖最后由 dcexpert 于 2021-9-17 11:27 编辑正在众筹的 python 学习图书 563323 这本书由童谣和童话故事组成，旁边有漂亮的整页插图。为什么是独一无二的？这些经典故事 ......; dcexpert MicroPython开源版块

keil汇编编程出错，解决不了: 程序如下： ORG 0000H LJMP START ORG 0003H LJMP EXT0 ORG TIM0 START: ......; w505024 51单片机

中国互联网手机造梦者:小米算成功了吗

小米算成功了吗　　40亿美元估值是否被夸大？500万的年销量真的没有悬念？中国第一部互联网手机的造梦者会不会成为先烈？　　《环球企业家》记者唐小薇侯继勇　　中国众多抢入手机行业的互联网公司们现在心情一定很矛盾：既希望小米手机(微博)能够成功，以证明以互联网的思路做手机是可行的；但又本能地不希望看到它这么快地成为率先成功的那个幸运儿。　　6月25日晚，小米手机突破300万台销量的...[详细]
泛华恒兴参加华南自动化展货架、系统产品齐亮相

作为致力于为各行业用户提供专业测试测量解决方案和成套检测设备的高新技术企业，北京泛华恒兴科技有限公司（简称：泛华恒兴）参加了2012年深圳华南自动化展，并参加了中国电源学会电源技术分会活动，这也是泛华首次有规模地参加华南市场的大型展会。泛华恒兴展台会上，由泛华恒兴推出的全新的系统级产品——电源自动化测试台高调亮相。电源自动化测试台倡导可靠、精准、自动、高效的电源测试，已...[详细]
基于网络技术的多电梯远程监控系统设计方案

　　伴随着城市经济的迅猛发展，电梯作为一种垂直交通工具，它的应用日益广泛。然而电梯的故障检测和及其维护，特别是电梯远程监控的作用就显得极为重要。但是国内在用的大多数电梯由于不能及早的预测电梯的运行故障而常常出现电梯困人、蹲底、冲顶、溜梯等突发情况。经研究发现，罪魁祸首是电梯内各种待测信号繁多，不便于布线且目前常用的2.5G 传输网络不能满足大量数据传输的需求等原因。因此，研究并开发基于zigbee...[详细]
基于ARM嵌入式IPCamera的设计与实现

0 前言随着社会的发展，人们对安全防范工作日益重视，监控产品也从以前只在重要单位使用发展到各个领域都在应用。监控产品的技术也从模拟向数字和网络技术发展。网络监控产品使用较多的是硬盘录像机，但价格比较高。有些场合对监控的要求并不高，也不需要录像，但有时又要在远程了解一下当地的画面，这时就希望使用一种低价的，又能实现远程操作的监控产品。所以就计划设计IPCamera（网络照相机），它能够接受网络...[详细]
芳香气体透过性检测方法

　　芳香气体广泛存在于食品、药品、化妆品和各种日化产品中，例如风味小吃、白酒、香料、中药材、膏药、香水、香皂、洗发水等等。与无机气体和水蒸气不同的是，多数芳香气体是由产品自身散发出来的，而且更是这些产品的重要品质和主要功能（有些也是唯一功能）。而对于这些产品来讲，芳香气体的存在起着极其重要的作用，散失或增加都会直接影响到产品的品质和销售，因而芳香气体种类以及浓度的保持成为衡量这些产品品质的重要指...[详细]
机顶盒付费：还没成熟就将褪去

在中国，付费电视的机顶盒领域还没待完全成熟，却已经要推出历史舞台了。随着付费电视方式的多样化，到2015年，接收43家已经开始布署多屏服务的全球最大付费电视运营商电视服务的设备中，将有49%是个人电脑(PC)、智能手机、平板等其它所谓的多屏设备，而2011年该比例只有18%。同时，机顶盒(STB)2015年占付费电视运营商设备的比例将降到只有51%，远低于2011年时的82%，如图所示。 ...[详细]
基于白光LED的一种新型光电器件—卡灯

LED 是light emitting diode (发光二极管)的缩写,是一种由半导体技术制成的电光源。LED的核心部分是由P型半导体和N型半导体组成的晶片,在P型半导体和N型半导体之间有一个过渡层,称为P2N结。在正向导通时,半导体中的多数载流子和少数载流子复合,释放出的能量以光子或部分以光子的形式发射出来,大量的光子形成光子流,即发光。P2N结加反向电压时,少数载流子难以注入,故不发...[详细]
日本计划将统一国内智能电视基本技术规格

据日本媒体报道，为了推动智能电视的普及，日本总务省将与国内电视机制造商、通讯公司等联合开发智能电视基本技术规格。　　日本总务省表示，新一代智能电视应具备面向各类制造商及软件公司的开放式技术标准。一旦各个公司都采用了通用的统一技术规格，那么连接不同品牌和系统的各种设备便能共通，很大程度上提高了便利度。　　为推进智能电视基本技术规格的统一，日本总务省计划在未来两年内与电视行业从业者展开...[详细]
深圳亿光P6室内led全彩屏进驻西藏山南地区国税局

2012-7-5日从西藏政治经济文化中心-山南地区传来喜讯，由深圳亿光科技有限公司（www.ledplay.com.cn）设计,生产,安装，位于山南地区国家税务局行政大厅的P6室内全彩LED屏成功点亮，运行稳定。据现场安装调试工程师介绍，LED显示屏安装工作经过了充分的准备协调工作，打开LED显示屏开关后未经任何额外辅助调试即以最佳的运行状态展现在用户的面前。现场协助安装的甲方工作人员对亿光LE...[详细]
四线测量技术测量超导体的电阻

　　在极低的温度下，某些金属和合金失去其对电流的电阻变成超导体。超导体的转变温度和临界电流密度是两个经常要测量的参数。超导体的转变温度是材料的电阻从有限数值变为零的温度。临界电流密度则是在特定的温度和磁场条件下，材料变成电阻性之前所能载荷的最大电流密度。这两个参数越高，超导体就越好。确定这两个参数需要测量很小的电阻，所以纳伏表和可程控的电流源对于进行精密的测量工作是非常重要的。　　...[详细]
连接器耐久性：汽车内部连接系统的核心

汽车制造商对其供应基地的要求越来越高，这对于汽车零配件供应商来说已经是一件众所周知的事情。就连接器供应商而言，这意味着对产品的性能、稳定性和成本的要求更加严格。供应商只有不断革新产品及工艺，满足客户的这些需求，才能处于优势地位。一辆典型轻型汽车大约有1500个连接点，其中50%到60%用于关键的配电功能。汽车连接器被用于日益恶劣的环境，包括温度（低至零下40°C，高达零上155°C）、振动、氧...[详细]
基于DSP的16通道声发射同步数据采集电路设计

摘要：针对煤岩声发射信号监测系统的需求，采用16位定点DSP芯片TMS320VC5509A和高精度A／D转换器ADS1278设计了一种具有24位分辨率、16通道同步数据采集功能的数据采集电路。控制接口采用I2C接口扩展I／O的方式实现，数据接口采用McBSP接口以帧同步方式实现，2片ADS1278采用菊花链的方式级联。给出了硬件电路、底层软件和测试结果，该数据采集电路具有接口简单、高性能、低...[详细]
3G 到 4G：跟老爸的移动基础设施说拜拜

移动接入互联网时代已经到来，其将在整体全新要求趋势下快速改变移动运营商的业务及基础设施需求。我们需要 4G LTE 来满足无线有效负载需求的快速增长，避免通话中断、下载失败以及视频中断等问题。那么，运营商怎么才能为这些多样化新型无线数据包提供可靠服务以满足用户需求并实现赢利呢？当然是转型。无线技术到了必须进行无线宽带转型的时候了。今后几年随着技术转型的完成，所有移动运营商的同构宏基站与小型基...[详细]
温补晶振补偿电压自动测试系统

　　温度补偿石英晶体振荡器(TCXO)由于具有较高的频率稳定度，作为一种高精度频率源被广泛地应用于通讯系统、雷达导航系统、精密测控系统等。温补晶振由石英晶体振荡电路和温度补偿网络两部分组成。其中，温度补偿网络的优化设计对于改善温补晶体振荡器的温频特性，提高振荡器的频率精度具有重要意义。　　1 温补晶振温度补偿原理　　温补晶振由石英晶体振荡电路和温度补偿网络两部分组成。典型的温补晶...[详细]
国务院发布新能源车产业规划 2020年累计产销5百万辆

7月9日，国务院正式发布《节能与新能源汽车产业发展规划》，规划称新能源汽车产业发展将以纯电驱动为新能源汽车发展和汽车工业转型的主要战略取向，当前重点推进纯电动汽车和插电式混合动力汽车产业化。此外，规划还对新能源汽车产业发展目标做出了具体要求，首先，在销量上，到2015年，纯电动汽车和插电式混合动力汽车累计产销量力争达到50万辆；到2020年，纯电动汽车和插电式混合动力汽车生产能力达200...[详细]

器件捷径: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

热门器件

开源项目推荐更多

热门活动更多

热门文章更多

技术资料推荐更多