Preliminary Data Sheet
PT7V4050
PLL with quartz stabilized VCXO
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Features
• PLL with quartz stabilized VCXO
• Loss of signals alarm
• Return to nominal clock upon LOS
• Input data rates from 8 kb/s to 65 Mb/s
• Tri-state output
• User defined PLL loop response
• NRZ data compatible
• Single +5.0V power supply
General Description
The device is composed of a phase-lock loop with an
integrated VCXO for use in clock recovery, data re-
timing, frequency translation and clock smoothing
applications in telecom and datacom systems.
Crystal Frequencies Supported:
12.000~65.536 MHz
Block Diagram
CLKIN
DATAIN
HIZ
Phase Detector &
LossOf Signal
Circuit
RCLK
RDATA
LOS
PHO
VC
LOSIN
CLK1
VCXO
Divider
CLK2
OPOUT
OPN
Op
Amp
OPP
Ordering Information
PT7V4050
Device Type
16-pin clock recovery
Package Leads
T: Thru-Hole
G: Surface Mount
M: Metal Can
CLK2 Divider
A: Divide by 2
E: Div ide by 32
B: Divide by 4
F: Divide by 64
C: Divide by 8
G: Divide by 128
D: Divide by 16
H: Divide by 256
K: Disable
T
B
C
G
A
51.840 / 25.920
CLK2 Frequency
module
CLK1 Frequency
Power Supply
A: 5.0V
C: ± 20ppm
F: ±32ppm
G:
±
50ppm
H:
±
100ppm
Temperature Range
C: 0
°
C to 70
°
C
T: -40
°
C to 85
°
C
12.000
16.128
18.432
22.579
28.000
34.368
44.736
51.840
54.000
Frequencies using at CLK1 (MHz)
12.288
12.624
13.00
16.000
13.384
16.777
16.896
17.920
18.936
20.000
20.480
22.1184
24.586
30.720
38.880
47.457
65.536
60.000
24.704
32.000
40.000
49.152
19.440
61.440
25.000
32.768
41.2416
49.408
35.328
62.208
27.000
33.330
41.943
50.000
40.960
62.500
PT0125(05/03)
1
Ver:0
Preliminary Data Sheet
PT7V4050
PLL with quartz stabilized VCXO
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Pin Configuration
VC
OPN
OPOUT
OPP
LOSIN
PHO
DATAIN
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
CLK1
HIZ
CLK2
RDATA
RCLK
LOS
CLKIN
Pin Description
Pin No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
VC
Type
I
Description
Control voltage input to internal voltage controlled crystal oscillator (VCXO).
Negative input terminal to internal operational amplifier.
Output terminal of internal operational amplifier.
Positive input terminal to internal operational amplifier.
TTL input. When LOSIN is set to HIGH, VC disabled, and when set to LOW, VC to
VCXO are enabled. (Internal pull-down resistor)
Output signal of phase detector.
TTL input. Input data stream to phase detector.
Ground.
TTL input. Input clock to phase detector.
Signal loss indication for DATAIN, high active.
Output recovered clock.
Output recovered data stream.
Output clock with divided function.
TTL input. When HIZ is set to LOW, the device is in standby state and the outputs are
set to high impedance. (Internal pull-up resistor)
Output clock of internal VCXO frequency.
5V power supply
OPN
OPOUT
OPP
LOSIN
PHO
DATAIN
GND
CLKIN
LOS
RCLK
RDATA
CLK2
HIZ
CLK1
V
CC
I
O
I
I
O
I
G
I
O
O
O
O
I
O
P
Notes:
1. LOSIN input sets to HIGH, VC is disabled and the VCXO returns to it’s nominal center frequency. When sets to LOW, VC to
VCXO is enabled.
2. LOS output sets to HIGH, if no transitions are detected at DATAIN after 256 clock cycles. LOS output sets to LOW as soon
as a transition occurs at DATAIN.
3. HIZ input sets LOW, output pins CLK1, CLK2, RCLK, and RDATA buffers are set to high-impedance state. When set to logic
high or no connection, the device functions and output pins CLK1, CLK2, RCLK, and RDATA etc. are active.
PT0125(05/03)
2
Ver:0
Preliminary Data Sheet
PT7V4050
PLL with quartz stabilized VCXO
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested)
Note:
Stresses greater than those listed under MAXIMUM
Storage Temperature ........................................................... -55
o
C to +125
o
C
RATINGS may cause permanent damage to the
Power Supply Voltage .................................................................. -0.5 to +7V
device. This is a stress rating only and functional
Input High Voltage ......................................................................... +7V Max. operation of the device at these or any other condi-
Input Low Voltage ......................................................................... -0.5V Min. tions above those indicated in the operational sec-
Input ESD Protection ..................................................................2000V Min. tions of this specification is not implied. Exposure
to absolute maximum rating conditions for extended
periods may affect reliability.
DC Electrical Characteristics
Symbol
V
CC
I
LEAK
V
TIH
V
TIL
V
OH1
V
OL1
V
OH2
V
OL2
I
PULLUP
I
PULLDOWN
I
CC
T
A
Parameters
Supply Voltage
Input Leakage Current
TTL Input High Voltage
TTL Input Low Voltage
Output High Voltage for CLK1
& 2, RCLK&RDATA
Output Low Voltage for CLK1
& 2, RCLK&RDATA
Output High Voltage for LOS
Output Low Voltage for LOS
Input Pull up Current for HIZ
Input Pull down Current for
LOSIN
Maximum Supply Current
Ambient Temperature
Ioh = -8mA
Iol = 8mA
Ioh = -3mA
Iol = 3mA
-160
50
Full Active
-40
60
85
2.4
0.4
2.4
0.4
0~V
DD
Conditions
Min
4.5
-10
2
0.8
Max
5.5
10
Units
V
µ
A
V
V
V
V
V
V
µ
A
µ
A
mA
o
C
PT0125(05/03)
3
Ver:0
Preliminary Data Sheet
PT7V4050
PLL with quartz stabilized VCXO
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AC Electrical Characteristics
Parameter
Input NRZ Data Rates
Input RZ Data and Clock Rates
Nominal Output Frequency
Clock Output 1
Clock Output 2
Transition Times:
Rise Time (0.5V to 2.5V)
Fall Time (2.5V to 0.5V)
Symmetry or Duty cycle (VS = 1.4V)
CLK1
CLK2
RCLK
Control Voltage Bandwidth (-3 dB,VC =
0.5V
CC
)
Sensitivity @ VC = V
CC
/2
Nominal Output Frequency on Loss of Signal:
Clock Output 1 & 2
Phase Detector Gain
Symbol
DATAIN
DATAIN
CLK1
CLK2
t
R
t
F
SYM 1
SYM 2
RCLK
BW
∆
F/
∆
VC
Min
0.008
0.008
12.00
CLK1 /256
0.5
0.5
40
45
40
Typical
Max
65.536
32.768
65.536
CLK1 /2
5
5
60
55
60
Unit
M b/s
M b/s
MHz
MHz
ns
ns
%
%
%
kHz
ppm/V
20
100
-75
-75
0.53
x Data
Density
75
75
CLK1
CLK2
KD
ppm from fo 1
ppm from fo 2
V/rad
PT0125(05/03)
4
Ver:0
Preliminary Data Sheet
PT7V4050
PLL with quartz stabilized VCXO
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Packaging Information
16-pin SMD (G)
20.32
10.16
2.54
4.15
1.73
1.2
20.32
10.16
PT0125(05/03)
10.16
6.7
5
Ver:0
FPGA/CPLD
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