2. Parameter verified during line and load regulation tests. Regulation is specified for 10% to 100% loading on all outputs.
3. Auxiliary output regulation is not maintained if main output load is less than 10%.
4. Auxiliary outputs require at least 10% loading for specified regulation. Voltage may increase at lighter loads and is ultimately limited by overvoltage zener diodes.
5.Unless otherwise specified, “Rated” load is 20W on the main (+5 volt) output and 15 watts each on the auxiliary (±15 volt) outputs. Load currents of up to 5A and ±1.5A on the main
and auxiliary outputs respectively are acceptable as long as the total output power does not to exceed 50 watts. Values in [ ] brackets reflect “-H" option SEE hardened version
performance. The "-H" option incorporates alternative FET technologies providing a >82 MeV•cm2 /mg (Gold Ion) SEE capability to the design.
6. Guaranteed for a D.C. to 20MHz bandwidth. Tested using a 20kHz to 10MHz bandwidth.
7. Capacitive load may be any value from 0 to the maximum limit without compromising dc performance. A capacitive load in excess of the maximum limit may interfere with the
proper operation of the converter’s overload protection, causing erratic behavior during turn-on.
8. Overload power dissipation is defined as the device power dissipation with the load set such that VOUT = 90% of nominal.
9. Load step transition time ? 10
μs.
10. Recovery time is measured from the initiation of the transient to where VOUT has returned to within ±1% of its steady state value.
11. Line step transition time ? 100
μs.
12. Turn-on delay time from either a step application of input power or a logic low to a logic high transition on the inhibit pin (pin 3) to the point where VOUT = 90% of nominal.
13. Load Regulation relative to output voltage at 50% rated load.
14. Line Regulation relative to output voltage at 120Vdc input.
15. For operation at temperatures between +85°C and +125°C, derate power linearly from 50 watts to zero. Parameter limits are not guaranteed.
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FPGA/CPLD
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