IEEE1394 to ATA/ATAPI Native Bridge
F
EATURES
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S400 (50 Mbytes/s) compliant 1394-1995 Link and
Transaction layers
Compatible with 1394-1995 and 1394A Phys.
Microsoft Win98-Second Edition, Win2000 and Apple
MacOS generic driver support
SBP-2 Target Revision 4 compliant interface
Fully ATA-5 compliant (see T13-1321D)
Support for UDMA5 (ATA100)
Sustained data transfer of 35 MB/s
Supports PIO modes 0 to 4, DMA modes 0 to 2 and
Ultra DMA modes 0 to 5
ORB co-processor to accelerate translation of ORBs
to ATAPI commands
Supports ORB chaining for increased performance
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OXFW911
Data Sheet
High performance ATA command translation in
firmware using Reduced Block Command (RBC) set
Integrated 32-bit RISC processor (ARM7TDMI) with
on-chip scratch RAM
Optional External Serial ROM interface for
configuration data, user serial number, etc.
Integrated 512kb Flash memory
Blank Flash memory programming feature via 1394
bus
Firmware and Flash Programming Utilities supplied by
Oxford Semiconductor
3.3 Volts operation
Low Power CMOS
Ultra-thin 128-TQFP package (14 x 14 x 1 mm)
D
ESCRIPTION
The OXFW911 is a high-performance 1394 to
ATA/ATAPI (IDE) native bridge with an integrated target
Serial Bus Protocol (SBP-2 ) controller.
By supporting
the SBP-2 protocol, the device can use generic SBP-2
drivers available in the Microsoft Windows 98SE, Microsoft
Windows 2000, Microsoft Millennium and Apple MacOS
(8.4 to 9.04) operating systems. MacOS support also
includes booting from Firewire disk.
The device is ideally suited for smart-cable or tailgate
interface applications for removable-media drives, compact
flash card readers, CD-ROM, CD-R, CD-RW, DVD-ROM,
DVD-RAM and hard disk drives, allowing IDE drives to be
connected to a 1394 serial bus in a plug-and-play fashion.
Both ATA and ATAPI devices are supported using the
same firmware.
This highly integrated device offers a two-chip solution to
native bridge applications using an external 1394 PHY. The
device is compatible with both 1394-1995 and 1394A
PHYs.
The LINK controller complies with 1394-1995 and 1394A
specifications. The 1394 transaction layer and SBP-2
protocol is implemented using a combination of the
ARM7TDMI (low-power 32-bit RISC processor), an ORB
(Operational Request Block) hardware co-processor and a
high performance buffer manager.
The buffer manager has a RAM bandwidth of 800Mbps. It
provides storage for 1394 and ATA/ATAPI packets,
Oxford Semiconductor Ltd.
25 Milton Park, Abingdon, Oxon, OX14 4SH, UK
Tel: +44 (0)1235 824900
Fax: +44(0)1235 821141
automatically storing them and passing them to the
appropriate destinations, without any intervention from the
processor. It also provides storage and manages the
sequencing of ORB fetching to reduce latency and improve
data throughput.
The configuration data including the IEEE OUI
(Organisational Unique Identifier) and device serial number
is stored in the Flash ROM which may be uploaded from
the 1394 bus, even when blank. The device also facilitates
firmware uploads from the 1394 bus.
The ORB co-processor translates ORBs as defined in the
SBP-2 protocol into ATA/ATAPI commands, and
automatically stores error/status messages at an address
specified by the host.
Concurrent operation of the ATA/ATAPI and 1394
interfaces are facilitated using the high throughput buffer
manager where LINK, ATAPI manager and ARM7TDMI
can perform interleaved accesses to the on-chip RAM
buffer. The high performance processor ensures that no
significant latency is incurred. The ATA command
translation is performed in firmware to meet RBC (Reduced
Block Commands) standard, T10-1228D. The ATA/ATAPI
Manager supports PIO modes 0 to 4, DMA modes 0 to 2
and Ultra DMA mode 0 to 5 and provides the interface to
the IDE bus. It is compliant with T13-1321D, ATA-5
specification, as well as support for ATA100.
©
Oxford Semiconductor 2001
OXFW911 Data Sheet Revision 1.1 – Mar 2001
Part No. OXFW911-TQ-A
OXFORD SEMICONDUCTOR LTD.
OXFW911
C
ONTENTS
FEATURES ........................................................................................................................................1
DESCRIPTION ...................................................................................................................................1
CONTENTS........................................................................................................................................2
1
2
3
4
5
6
6.1
6.2
6.3
5.1
BLOCK DIAGRAM .......................................................................................................................3
PIN INFORMATION .....................................................................................................................4
PIN DESCRIPTIONS ....................................................................................................................5
OPERATING CONDITIONS ..........................................................................................................7
DC ELECTRICAL CHARACTERISTICS ........................................................................................7
I/O BUFFERS ........................................................................................................................................................................ 7
IDE INTERFACE ................................................................................................................................................................... 8
1394 LINK-PHY INTERFACE ............................................................................................................................................. 11
EXTERNAL PROCESSOR INTERFACE............................................................................................................................ 13
AC ELECTRICAL CHARACTERISTICS ........................................................................................8
7
8
9
TIMING WAVEFORMS...............................................................................................................14
PACKAGE INFORMATION ........................................................................................................29
ORDERING INFORMATION .......................................................................................................29
NOTES ............................................................................................................................................31
CONTACT DETAILS.........................................................................................................................32
DISCLAIMER ...................................................................................................................................32
Data Sheet Rev 1.1
Page 2
OXFORD SEMICONDUCTOR LTD.
OXFW911
3
P
IN
D
ESCRIPTIONS
Dir
1
I/O
I/O
I
O
IU
O
T_I/O
T_O
T_O
T_O
T_O
T_IU
T_I/O
T_O
T_O
T_O
T_O
T_I
T_O
T_O
T_O
T_O
T_I
O
O
O
T_IU
IU
T_O
I
IU
VDD
VDD
Name
PD[7:0]
CTL[1:0]
PHYCLK
LREQ
LINKON
LPS
D[15:0]
A[16:0]
CS#[3:0]
OE#
WE#
INT#
ID[15:0]
IA[2:0]
ICS#[1:0]
IDE_OE#
IRESET
DMARQ
DIOW#
DIOR#
IORDY
DMACK#
INTRQ
GPO1
GPO2
GPO3
GPI
RESET#
CKOUT
TEST_SEL,
TEST[1:0]
UIF
AC VDD
DC VDD
Description
Phy-Link Data Bus
Phy-Link Control Bus
49.152 MHz clock sourced by PHY
Link Request
Requests link to power up when in a low power mode
Indicates to phy that link is powered and ready
ARM external data bus
ARM external address bus
ARM external chip selects. CS0# is always used for program
ROM.
ARM external output enable. Active when reading data from
external devices including program ROM
Write Enable. Active when writing to external devices
External ARM interrupt
IDE data bus
IDE address bus
IDE chip select. Used to select the Command Block or
Control Block registers.
IDE output enable. Only used when external buffering is
required to drive IDE data bus
IDE interface reset
IDE interface write strobe
IDE interface read strobe
1394 PHY-LINK interface
104, 105, 108, 109, 110, 111, 114,
115
116,117
119
121
102
103
ARM external interface
2, 3, 4, 5, 6, 9, 10, 11, 12, 13, 16,
17, 18, 19, 20, 24
35, 36, 37, 38, 41, 42, 43, 44, 45,
46, 49, 50, 51, 52, 53, 54, 60
123, 124, 27, 33
28
34
61
IDE interface
86, 82, 80, 78, 74, 72, 70, 66, 65,
69, 71, 73, 77, 79, 81, 85
99, 97, 98
101, 100
63
64
89
90
91
92
95
62
EEPROM interface
125
126
127
58
Miscellaneous Pins
56
128
22, 32, 31
57
Power and ground
2
15, 8, 40, 48, 59, 76, 94, 107, 113
30, 21, 23, 68, 84, 88, 120
Data Sheet Rev 1.1
General Purpose Output 1
General Purpose Output 2
General Purpose Output 3
General Purpose Input
Global reset for the OXFW911. Active Low.
Clock output. 49.152 MHz clock output.
‘100’ = NORMAL OPERATION. Other settings are for
foundry test purposes only.
Leave unconnected to use internal Flash, tie low to use only
external device
Supplies power to output buffers in switching (AC) state
Power supply. Supplies power to core logic, input buffers
and output buffers in steady state
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