64 Mbit SPI Serial Dual I/O Flash
SST25VF064C
SST25VF032B32Mb Serial Peripheral Interface (SPI) flash memory
Data Sheet
FEATURES:
• Single Voltage Read and Write Operations
– 2.7-3.6V
• Serial Interface Architecture
– SPI Compatible: Mode 0 and Mode 3
• Dual Input/Output Support
– Fast-Read Dual-Output Instruction
– Fast-Read Dual I/O Instruction
• High Speed Clock Frequency
– 80 MHz for High-Speed Read (0BH)
– 75 MHz for Fast-Read Dual-Output (3BH)
– 50 MHz for Fast-Read Dual I/O (BBH)
– 33 MHz for Read Instruction (03H)
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
– Active Read Current: 12 mA (typical @ 80 MHz) for
single-bit read)
– Active Read Current: 14 mA (typical @ 75MHz) for
dual-bit read)
– Standby Current: 5 µA (typical)
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks
– Uniform 64 KByte overlay blocks
• Fast Erase
– Chip-Erase Time: 35 ms (typical)
– Sector-/Block-Erase Time: 18 ms (typical)
• Page-Program
– 256 Bytes per page
– Single and Dual Input support
– Fast Page-Program time in 1.5 ms (typical)
• End-of-Write Detection
– Software polling the BUSY bit in Status Register
• Write Protection (WP#)
– Enables/Disables the Lock-Down function of the
status register
• Software Write Protection
– Write protection through Block-Protection bits in sta-
tus register
• Security ID
– One-Time Programmable (OTP) 256 bit, Secure ID
- 64 bit Unique, Factory Pre-Programmed identifier
- 192 bit User-Programmable
• Temperature Range
– Commercial = 0°C to +70°C
– Industrial: -40°C to +85°C
• Packages Available
– 16-lead SOIC (300 mils)
– 8-contact WSON (6mm x 8mm)
– 8-lead SOIC (200 mils)
• All devices are RoHS compliant
PRODUCT DESCRIPTION
The SST 25 series Serial Flash family features a four-wire,
SPI-compatible interface that allows for a low pin-count
package which occupies less board space and ultimately
lowers total system costs. SST25VF064C SPI serial flash
memory is manufactured with SST proprietary, high-perfor-
mance CMOS SuperFlash technology. The split-gate cell
design and thick-oxide tunneling injector attain better reli-
ability and manufacturability compared with alternate
approaches.
The SST25VF064C significantly improves performance
and reliability, while lowering power consumption. The
device writes (Program or Erase) with a single power sup-
ply of 2.7-3.6V. The total energy consumed is a function of
the applied voltage, current, and time of application. Since
for any given voltage range, the SuperFlash technology
uses less current to program and has a shorter erase time,
the total energy consumed during any Erase or Program
operation is less than alternative flash memory technolo-
gies.
The SST25VF064C device is offered in 16-lead SOIC (300
mils), 8-contact WSON (6mm x 8mm), and 8-lead SOIC
(200 mils) packages. See Figure 2 for pin assignments.
©2009 Silicon Storage Technology, Inc.
S71392-02-000
9/09
1
The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
64 Mbit SPI Serial Dual I/O Flash
SST25VF064C
Data Sheet
Address
Buffers
and
Latches
X - Decoder
SuperFlash
Memory
Y - Decoder
Control Logic
Page Buffer,
I/O Buffers
and
Data Latches
Serial Interface
CE#
SCK
SI/SIO
0
SO/SIO
1
WP#
RST#/HOLD#
1392 B1.0
FIGURE 1: Functional Block Diagram
©2009 Silicon Storage Technology, Inc.
S71392-02-000
9/09
2
64 Mbit SPI Serial Dual I/O Flash
SST25VF064C
Data Sheet
PIN DESCRIPTION
RST#/HOLD#
VDD
NC
NC
NC
NC
CE#
SO/SIO1
Top View
SCK
SI/SIO0
NC
NC
NC
NC
VSS
WP#
CE#
SO/SIO1
WP#
VSS
1
2
3
4
8
7
6
5
Top View
VDD
RST#/HOLD#
SCK
SI/SIO0
1392 8-WSON P1.0
CE#
1392 16-SOIC P1.0
1
2
3
4
8
VDD
RST#/HOLD#
SCK
SI
SO
WP#
VSS
Top View
7
6
5
1392 8-soic S3A P1.0
FIGURE 2: Pin Assignments for 16-Lead SOIC, 8-Contact WSON, and 8-Lead SOIC
TABLE 1: Pin Description
Symbol
SCK
Pin Name
Serial Clock
Functions
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock
input, while output data is shifted out on the falling edge of the clock input.
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
To transfer commands, addresses, or data serially into the device, or data out of the
device.
Inputs are latched on the rising edge of the serial clock.
Data is shifted out on the falling edge of the serial clock. These pins are for Dual I/O
mode.
The device is enabled by a high to low transition on CE#. CE# must remain low for
the duration of any command sequence.
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
To reset the operation of the device and the internal logic. The device powers on with
RST# pin functionality as default.
To temporarily stop serial communication with SPI Flash memory while device is
selected. This is selected by an instruction sequence. See “Reset/Hold Mode” page 5
for details.
To provide power supply voltage: 2.7-3.6V
T1.0 1392
SI
SO
SIO[0:1]
Serial Data Input
Serial Data Output
Serial Data Input/
Output for Dual I/O
Mode
CE#
WP#
RST#/HOLD#
Chip Enable
Write Protect
Reset
Hold
V
DD
V
SS
Power Supply
Ground
©2009 Silicon Storage Technology, Inc.
S71392-02-000
9/09
3
64 Mbit SPI Serial Dual I/O Flash
SST25VF064C
Data Sheet
MEMORY ORGANIZATION
The SST25VF064C SuperFlash memory array is orga-
nized in uniform 4 KByte erasable sectors with 32 KByte
overlay blocks and 64 KByte overlay erasable blocks.
The SST25VF064C supports both Mode 0 (0,0) and Mode
3 (1,1) of SPI bus operations. The difference between the
two modes, as shown in Figure 3, is the state of the SCK
signal when the bus master is in Stand-by mode and no
data is being transferred. The SCK signal is low for Mode 0
and SCK signal is high for Mode 3. For both modes, the
Serial Data In (SI) is sampled at the rising edge of the SCK
clock signal and the Serial Data Output (SO) is driven after
the falling edge of the SCK clock signal.
DEVICE OPERATION
The SST25VF064C is accessed through the SPI (Serial
Peripheral Interface) bus compatible protocol. The SPI bus
consists of four control lines; Chip Enable (CE#) is used to
select the device, and data is accessed through the Serial
Data Input (SI), Serial Data Output (SO), and Serial Clock
(SCK).
CE#
MODE 3
MODE 3
MODE 0
SCK
SI
SO
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
DON'T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
1392 F04.0
HIGH IMPEDANCE
FIGURE 3: SPI Protocol
©2009 Silicon Storage Technology, Inc.
S71392-02-000
9/09
4
64 Mbit SPI Serial Dual I/O Flash
SST25VF064C
Data Sheet
Reset/Hold Mode
The RST#/HOLD# pin provides either a hardware reset or
a hold pin. From power-on, the RST#/HOLD# pin defaults
as a hardware reset pin (RST#). The Hold mode for this pin
is a user selected option where an EHLD instruction
enables the Hold mode. Once selected as a hold pin
(HOLD#), the RST#/HOLD# pin will be configured as a
HOLD# pin, and goes back to RST# pin only after a power-
off and power-on sequence.
Reset
If the RST#/HOLD# pin is used as a reset pin, RST# pin
provides a hardware method for resetting the device. Driving
the RST# pin high puts the device in normal operating
mode. The RST# pin must be driven low for a minimum of
T
RST
time to reset the device. The SO pin is in high imped-
ance state while the device is in reset. A successful reset will
reset the status register to its power-up state (BPL, BUSY
and WEL = 0; BP3, BP2, BP1, and BP0 = 1). See Table 2
for default power-up modes. A device reset during an active
Program or Erase operation aborts the operation and data
of the targeted address range may be corrupted or lost due
to the aborted erase or program operation.
CE#
T
RECR
T
RECP
T
RECE
SCK
T
RST
RST#
T
RHZ
SO
SI
1292 F28.0
FIGURE 4: Reset Timing Diagram
TABLE 2: Reset Timing Parameters
Symbol
T
RST
T
RHZ
T
RECR
T
RECP
T
RECE
Parameter
Reset Pulse Width
Reset to High-Z Output
Reset Recovery from Read
Reset Recovery from Program
Reset Recovery from Erase
Min
100
105
100
10
1
Max
Units
ns
ns
ns
µs
ms
T2.1392
©2009 Silicon Storage Technology, Inc.
S71392-02-000
9/09
5
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