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TMC2193
10 Bit Encoder
Features
• Multiple input formats
– 24 bit RGB
– 20 bit CCIR601
– 10 bit CCIR656
– 10 bit Digital Composite
• Synchronization modes
– Master
– Slave
– Genlock
– CCIR656
• Subcarrier modes
– Free-run
– Subcarrier reset
– Genlock
– DRS-lock
• Ancillary Data Control (ANC)
• Pixel rates from 10 MHz to 15 MHz
• Programmable horizontal timing
• Programmable vertical blanking interval (VBI)
• Line-by-line pedestal enable
• Programmable pedestal height from -20 IRE to 20 IRE
• Programmable burst amplitude and phase
• Controlled edge rates for
– Sync
– Burst
– Active video
•
•
•
•
•
Programmable color space matrix
8:8:8 video reconstruction
Four 10 bit D/A’s with independent trim
Individual power down modes for each D/A
Multiple output formats
– RGB
– Y P
B
P
R
– Betacam
– S-video
– Composite
– Digital composite output
Pin-driven and data-driven, window keying
Closed Caption waveform generation (13.5 MHz only)
Sin(X)/X compensation filter
5 bit VBI line counter
3 bit field counter
Internal test pattern generation
– 100% Color Bars
– 75% Color Bars
– Modulated Ramp
•
•
•
•
•
•
Applications
• Broadcast Television
• Nonlinear Video Processing
Block Diagram
sync/mid
REFDAC
CBYP1
DAC1
INTERP.
Bl/Pb
Y
U
V
CHROMA
PROCESSOR
Rd/Pr
Ch
INTERP.
COMP2
CC
CVBS[9:0]
SYNC
INSERT
KEY
MIX
INTERP.
DAC
REF.
INTERP.
RREF1
CBYP2
DAC2
RREF2
CBYP3
DAC3
RREF3
CBYP4
DAC4
RREF4
PD[23:0]
PRE-
PROCESSOR
OL[4:0]
KEY
gr/y
bl/cb
OVERLAY rd/cr
MIXER
Gr/Y
Bl/Pb
Rd/Pr
COLOR
SPACE
MATRIX
SYNC
INSERT
Gr/Y
Comp
Y
FVHGEN
MPU
DCVEN
PDCIN/PDCOUT
RESET
SERB
D[7:0]
A[1:0]/SA[1:0]
LINE[4:0]
FLD[2:0]
CS/SCL
PXCK
HSOUT
VSOUT
R/W\/SDA
VREF
HSIN
VSIN
65-6294-01
REV. 1.0 3/26/03
TMC2193
PRODUCT SPECIFICATION
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Applications. . . . . . . . . . . . . . . . . . . . . . . . .1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . .1
10 Bit Encoder . . . . . . . . . . . . . . . . . . . . . . .1
LIst of Figures . . . . . . . . . . . . . . . . . . . . . . .3
LIst of Tables . . . . . . . . . . . . . . . . . . . . . . . .3
Pin Assignments . . . . . . . . . . . . . . . . . . . . .4
Pin Definitions . . . . . . . . . . . . . . . . . . . . . . .4
Functional Description . . . . . . . . . . . . . . . .7
Input Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Gamma Correction . . . . . . . . . . . . . . . . . . . . . . 9
Color Space Matrix . . . . . . . . . . . . . . . . . . . . . . 9
Synchronization Modes . . . . . . . . . . . . . . . . . 12
Propagation Delay . . . . . . . . . . . . . . . . . . . . . . 12
Blanking Control . . . . . . . . . . . . . . . . . . . . . . . 13
Pixel Data Control . . . . . . . . . . . . . . . . . . . . . . 13
Edge Shaping. . . . . . . . . . . . . . . . . . . . . . . . . . 13
Horizontal Programming. . . . . . . . . . . . . . . . . 14
Vertical Timing . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chrominance Processor . . . . . . . . . . . . . . . . .
Subcarrier Programming . . . . . . . . . . . . . . .
NTSC Subcarrier . . . . . . . . . . . . . . . . .
PAL Subcarrier . . . . . . . . . . . . . . . . . . .
PAL-M Subcarrier . . . . . . . . . . . . . . . . .
Subcarrier Synchronization. . . . . . . . . . . . .
SCH Phase Error Correction. . . . . . . . . . . .
Burst Envelope . . . . . . . . . . . . . . . . . . . . . .
Color-Difference Low-Pass Filters. . . . . . . .
23
23
23
23
23
24
24
25
25
Interpolation Filters . . . . . . . . . . . . . . . . . . . . . 27
x/Sin(x) Filter . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Output Data Formats. . . . . . . . . . . . . . . . . . . . 27
Digital Composite Output . . . . . . . . . . . . . . . . 28
Ancillary Data. . . . . . . . . . . . . . . . . . . . . . . . . . 28
Operating Modes. . . . . . . . . . . . . . . . . . . . . 29
Layering Engine. . . . . . . . . . . . . . . . . . . . . . . . 30
Overlay Mixer . . . . . . . . . . . . . . . . . . . . . . . 30
Hardware Keying . . . . . . . . . . . . . . . . . . . . . . . 31
Data Keying . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Parallel Microprocessor Interface . . . . . . . . . 31
Serial Control Port (R-Bus) . . . . . . . . . . . . . . . 33
Data Transfer via Serial Interface . . . . . . . . 33
Serial Interface Read/Write Examples . . . . 34
Control Register Map . . . . . . . . . . . . . . . . 35
Control Register Definitions . . . . . . . . . . 37
Absolute Maximum Ratings . . . . . . . . . . . 62
Operating Conditions . . . . . . . . . . . . . . . . 62
Electrical Characteristics . . . . . . . . . . . . . 64
Switching Characteristics . . . . . . . . . . . . 64
System Performance Characteristics . . . 65
Applications Discussion . . . . . . . . . . . . . 65
Layout Considerations . . . . . . . . . . . . . . . . . . 66
Output Low-Pass Filters . . . . . . . . . . . . . . . . . 69
Mechanical Dimensions . . . . . . . . . . . . . . 70
100-Lead MQFP . . . . . . . . . . . . . . . . . . . . . . . . 70
Sync and Pedestal Insertion. . . . . . . . . . . . . . 25
Pedestal Enable . . . . . . . . . . . . . . . . . . . . . 25
Pedestal Height . . . . . . . . . . . . . . . . . . . . . . 26
Sync and Blank Insertion . . . . . . . . . . . . . . 26
Closed Caption Insertion . . . . . . . . . . . . . . . .
Line Selection . . . . . . . . . . . . . . . . . . . . . . .
Parity Generation . . . . . . . . . . . . . . . . . . . .
Operating Sequence . . . . . . . . . . . . . . . . . .
26
26
26
26
Ordering Information . . . . . . . . . . . . . . . . 72
Life Support Policy . . . . . . . . . . . . . . . . . . 72
2
REV. 1.0 3/26/03
PRODUCT SPECIFICATION
TMC2193
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Input Formats . . . . . . . . . . . . . . . . . . . . . .7
24 bit Input Format . . . . . . . . . . . . . . . . . .7
CCIR656 Input Format . . . . . . . . . . . . . . .8
10 bit Input Format . . . . . . . . . . . . . . . . . .8
20 bit 4:2:2 Input Format . . . . . . . . . . . . .8
20 bit 4:4:4 Input Format . . . . . . . . . . . . .8
Gamma Curves . . . . . . . . . . . . . . . . . . . .9
Propagation Delay through the
Encoder . . . . . . . . . . . . . . . . . . . . . . . . .12
Horizontal Timing . . . . . . . . . . . . . . . . . .15
Horizontal Timing – Vertical Blanking . . .15
Horizontal Timing – 1st Half-line. . . . . . .16
Horizontal Timing – 2nd Half-line . . . . . .16
NTSC Vertical Interval . . . . . . . . . . . . . .17
PAL Vertical Interval . . . . . . . . . . . . . . . .19
PAL-M Vertical Interval . . . . . . . . . . . . . .21
Burst Envelope . . . . . . . . . . . . . . . . . . . .25
Gaussian Filter Response . . . . . . . . . . .25
Interpolation Filter. . . . . . . . . . . . . . . . . .27
Interpolation Filter – Passband
Detail . . . . . . . . . . . . . . . . . . . . . . . . . . .27
X/SIN(X) Filter . . . . . . . . . . . . . . . . . . . .27
Layering Engine . . . . . . . . . . . . . . . . . . .30
Overlay Outputs . . . . . . . . . . . . . . . . . . .31
Data Keying . . . . . . . . . . . . . . . . . . . . . .31
Microprocessor Parallel Port –
Write Timing . . . . . . . . . . . . . . . . . . . . . .32
Microprocessor Parallel Port –
Read Timing . . . . . . . . . . . . . . . . . . . . . .32
Serial Port Read/Write Timing . . . . . . . .33
Serial Interface – Typical Byte
Transfer. . . . . . . . . . . . . . . . . . . . . . . . . .34
Serial Interface – Chip Address . . . . . . .34
Typical Analog Reconstruction Filter . . .65
Overall Response . . . . . . . . . . . . . . . . . .65
Typical Layout . . . . . . . . . . . . . . . . . . . . .67
ST-163E Layout . . . . . . . . . . . . . . . . . . .68
Pass Band . . . . . . . . . . . . . . . . . . . . . . .69
Stop Band. . . . . . . . . . . . . . . . . . . . . . . .69
2T Pulse . . . . . . . . . . . . . . . . . . . . . . . . .69
Group Delay . . . . . . . . . . . . . . . . . . . . . .69
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
CSM Coefficient Range . . . . . . . . . . . .
Expected Output Values for the
CSM with YCBCR Inputs . . . . . . . . . . .
Expected Output Values for the
CSM with RGB Inputs. . . . . . . . . . . . . .
Coefficient sets YCBCR inputs . . . . . . .
Coefficient sets YCBCR inputs . . . . . . .
PDC Edge Control . . . . . . . . . . . . . . . .
Horizontal Line Equations. . . . . . . . . . .
Horizontal Timing Specifications. . . . . .
Vertical Interval Timing
Specifications . . . . . . . . . . . . . . . . . . . .
Default Horizontal Timing
Parameters . . . . . . . . . . . . . . . . . . . . . .
NTSC Field/Line Sequence and
Identification . . . . . . . . . . . . . . . . . . . . .
PAL Field/Line Sequence and
Identification . . . . . . . . . . . . . . . . . . . . .
PAL-M Field/Line Sequence and
Identification . . . . . . . . . . . . . . . . . . . . .
Standard Subcarrier Parameters . . . . .
Line by Line Pedestal Enable . . . . . . . .
Closed Caption Line Selection . . . . . . .
D/A Outputs . . . . . . . . . . . . . . . . . . . . .
Ancillary Data Format . . . . . . . . . . . . . .
Ancillary Data Control – Phase . . . . . .
Ancillary Data Control Frequency. . . . .
Field Identification and Subcarrier
Reset Modes . . . . . . . . . . . . . . . . . . . .
Layering and Keying Modes . . . . . . . . .
Overlay Address Map . . . . . . . . . . . . . .
Parallel Port Control . . . . . . . . . . . . . . .
Serial Port Addresses. . . . . . . . . . . . . .
Control Register Map . . . . . . . . . . . . . .
10
11
11
11
11
13
14
15
16
17
18
20
22
24
25
26
27
28
29
29
29
30
31
32
33
35
REV. 1.0 3/26/03
3
TMC2193
PRODUCT SPECIFICATION
Pin Assignments
100
1
81
80
Pin
1
2
3
4
5
6
7
8
9
10
11
12
30
31
50
51
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Function
VDDA
DAC4
CBYP4
AGND
DAC3
CBYP3
VDDA
RREF3
AGND
DAC2
CBYP2
VDDA
RREF2
AGND
DAC1
CBYP1
VDDA
RREF1
REFDAC
KEY
OL4
OL3
OL2
OL1
OL0
DGND
PD23
PD22
PD21
PD20
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Function
PD19
PD18
PD17
PD16
PD15
PD14
PD13
PD12
VDD
DGND
PD11
PD10
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
Pin
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Function
PD1
PD0
DGND
VDD
VSIN
HSIN
DCVEN
SER
CSVSCL
R/WVSDA
A1/SA1
A0/SA0
D7
D6
D5
D4
D3
D2
D1
D0
DGND
VDD
PDC
HSOUT
VSOUT
LINE4
LINE3
LINE2
LINE1
LINE0
Pin
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Function
FLD2
FLD1
FLD0
CVBS9
CVBS8
CVBS7
CVBS6
CVBS5
CVBS4
CVBS3
CVBS2
CVBS1
CVBS0
RESET
PXCK
VDD
DGND
VREF
RREF4
AGND
65-6294-14
Pin Definitions
Pin Name
DCVEN
Pin Number
57
Value
TTL
Description
Digital CVBS Output Enable.
When DCVEN is LOW, the
Comp2 output prior to the D/A is routed to D7-0, FLD2-1
providing a digital composite output. When DCVEN is HIGH,
D7-0 and FLD2-1 operate in their normal mode.
Horizontal Sync Input.
When operating in slave, Genlock, or
DRS-Lock the TMC2193 will start a new horizontal line with
each falling edge of HSIN.
Hard Key selection.
When the control register bit HKEN is set
HIGH and the hardware KEY pin is high, the video data
considered to be the foreground. is routed to the COMP2
output. This control signal is data aligned so that the pixel that is
present on the PD port when KEY signal is latched is at the
midpoint of the key transition. When HKEN is LOW, Key is
ignored.
CLOCK, SYNC, & CONTROL INPUTS (6 pins)
HSIN
56
TTL
KEY
20
TTL
4
REV. 1.0 3/26/03
PRODUCT SPECIFICATION
TMC2193
Pin Definitions
(continued)
Pin Name
PXCK
Pin Number
95
Value
TTL
Description
Pixel Clock Input.
PXCK is a clock signal that period is twice
the sample rate of the pixel data. The operating range is 20 to
30 MHz. The clock is internally divided by 2 to generate the
internal pixel clock, PCK. PXCK drives the entire TMC2193
except the asynchronous microprocessor interface.
Master Chip Reset.
When LOW, All outputs are tri-stated and
the internal state machines and control registers are reset. At
rising edge of RESET, all outputs are active, the preset values
will be loaded into the control registers and the internal states
machines start to operate.
Vertical Sync Input.
When operating in slave, Genlock, or
DRS-Lock the TMC2193 will start a new vertical field with each
falling edge of VSIN that is coincident with HSIN.
Field Identifier.
Field Identifier outputs the current field number.
For all video standards the field identifier will cycle through the
eight counts.
Horizontal Sync Output.
The alignment of HSOUT to the pixel
data port or DCVBS port is controlled by control register
TSOUT.
Vertical Blanking Interval Line Identifier.
LINE identifies the
current line number for the first 31 lines. If the line count is
greater than 31 then LINE is 11111b. The first line with a vertical
serration is considered to be line 0.
Pixel Data Control.
When PDCDIR = LOW:
At a rising edge, The next pixel starts a
controlled ramp of the PD data. At a falling edge, the pixel prior
is the last PD used in the ramp. The rising edge is determined
by the PDCCNT control register, the falling edge of PDC is
determined by the horizontal timing registers.
When PDCDIR = HIGH:
PDCIN is used to override the internal
PDC. When HIGH, the internal PDC controls the blank and
unblank window. When LOW, the video remains blanked
regardless of the internal PDC. All edges have the same ramp
control as the internal PDC.
VSOUT
75
TTL
Vertical Sync Output.
The alignment of VSOUT to the pixel
data port or DCVBS port is controlled by control register
TSOUT.
Composite Data Input
Overlay Control
Component Data Input
Selectable sync only or midpoint reference D/A
Composite or Green D/A
Luma or Blue D/A
Chroma or Red D/A
Composite D/A with optional keying
5
RESET
94
TTL
VSIN
55
TTL
SYNC & CONTROL OUTPUTS (11 pins)
FLD[2:0]
81–83
TTL
HSOUT
74
TTL
LINE[4:0]
76–80
TTL
PDC
73
TTL
DATA INPUTS (39 pins)
CVBS[9:0]
OL[4:0]
PD[23:0]
Ref. DAC
DAC1
DAC2
DAC3
DAC4
REV. 1.0 3/26/03
84–93
21–25
27–38, 41–52
19
15
10
5
2
TTL
TTL
TTL
0.675Vp-p
1.35Vp-p
1.35Vp-p
1.35Vp-p
1.35Vp-p
ANALOG INTERFACE – Video Out (5 pins)
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