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TMC22071A
Genlocking Video Digitizer
Features
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Fully integrated acquisition
3-channel video input multiplexer
Two-stage video clamp
Automatic gain adjustment
Sync detection and separation
Pixel and subpixel adjustment of HSYNC-to-Video
timing
Genlock to NTSC or PAL inputs
Clock generation
8-bit video A/D converter
Microprocessor interface
Line-locked pixel rates
- 12.27 MHz NTSC
- 13.5 MHz NTSC or PAL
Direct interface to TMC22x9x encoders
Built-in circuitry for crystal oscillator
No tuning or external voltage reference required
68 Lead PLCC or 100 Lead MQFP package
Description
The TMC22071A Genlocking Video Digitizer converts stan-
dard baseband composite NTSC or PAL video into 8-bit dig-
ital composite video data. It extracts horizontal and vertical
sync signals and generates a pixel clock for the on-board
8-bit A/D converter and a 2x clock for the transfer of data to
subsequent video processing decoding or encoding with the
TMC22x5y Video Decoder or TMC22x9x Digital Video
Encoder family. It also measures the color subcarrier phase
and frequency and provides this data to the Encoder (for gen-
locked color NTSC or PAL encoding), or a frame buffer (for
frame capture) over the digital composite video port.
The TMC22071A includes a three-channel video input mul-
tiplexer, analog clamp, variable gain amplifier, and digital
back porch clamp. The on-board oscillator circuitry gener-
ates the clock from a 20 MHz crystal or the clock source may
be an external oscillator. It is programmable over a micro-
processor interface for NTSC or PAL operation. No external
component changes and no production tuning or service
adjustments are ever required.
The TMC22071A is fabricated in an advanced CMOS
process, and is packaged in a 68 Lead PLCC or 100 Lead
MQFP. Its performance is guaranteed from 0°C to 70°C.
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Applications
• Frame grabber
• Digital VCR/VTR
• Desktop video
Block Diagram
BACK PORCH
CLAMP
VIN1
MUX
VIN2
VIN3
D/A
LOWPASS
FILTER
ANALOG
CLAMP
GAIN
A/D
SUBCARRIER
PHASE-LOCKED
LOOP
DATA
SELECTOR
CVBS7-0
SYNC
SEPARATOR
GVSYNC
GHSYNC
D/A
CONTROL
+1.2V
DIRECT
DIGITAL
SYNTHESIZER
HORIZONTAL
PHASE-LOCKED
LOOP
PXCK
LDV
VALID
PFD IN
CLK IN
COMP
VREF
RT
EXT PXCK
R/W
INT
CLK
OUT
DDS
OUT
PXCK SEL
RESET
D0
A0
CS
RB
CBYP
65-22071-01
MICROPROCESSOR
INTERFACE
ANALOG INTERFACE
DDS/PIXEL CLOCK INTERFACE
Rev. 1.0.5
TMC22071A
PRODUCT SPECIFICATION
Functional Description
The TMC22071A is a fully-integrated genlocking video A/D
converter which digitizes NTSC or PAL baseband composite
video under program control. It accepts video on three
selectable input channels, adjusts gain, clamps to the back
porch, and digitizes the video at a multiple of the horizontal
line frequency. It extracts horizontal and vertical sync, mea-
sures the subcarrier frequency and phase (relative to the sam-
pling clock), and provides the data along with digital
composite video data over an 8-bit digital video port. Two
sync outputs (GHSYNC and GVSYNC) are also provided. It
generates 1x (LDV) and 2x (PXCK) pixel clocks for data
transfer. PXCK also serves as a master clock for the compan-
ion TMC22x9x Encoders and TMC22x5y decoders.
Operating parameters are set up via a serial microprocessor
port. Internal or external voltage reference operation is avail-
able
amplitudes during initial genlock acquisition, and then
(optionally) holds the gain constant. This results in a stable
picture under variable signal conditions.
Improperly terminated or weak video signals are handled in
the TMC22071A by a selectable gain of +1.0 or +1.5. The
higher gain can amplify a doubly-terminated signal which is
reduced in amplitude by 2/3.
If the input signal levels are well controlled, the automatic
gain adjustment can be disabled and the gain held at its nom-
inal value (unity or 1.5X).
Analog-to-Digital Converter
The TMC22071A contains a high-performance 8-bit A/D
converter. Its gain and offset are automatically set as a part of
the automatic gain adjustment process during initial signal
acquisition, and require no user attention.
The reference voltages to the A/D converter are set up by
internal D/A converters under automatic control during gen-
lock acquisition. These voltages determine the gain and off-
set of the A/D converter with respect to the video level
presented at its input.
Timing
The TMC22071A operates from an internally-synthesized
clock, PXCK, which runs at twice the pixel data rate. The
nominal pixel rates may be set to 12.27 Mpps for NTSC and
13.5 Mpps for NTSC and PAL. Customers requiring 14.75 or
15 Mpps PAL operation should consult factory.
Low-Pass Filter
The digitized composite video stream is digitally low-pass
filtered to remove chrominance components from the sync
separator. Filtering provides robust operation by optimizing
the signal-to-noise ratio of the synchronizing/blanking por-
tion of the video, improving the accuracy of the back porch
blanking level detector.
A digital sync separator provides the output sync signals,
GHSYNC and GVSYNC, and times internal operations.
Video Input
Three high-impedance video inputs are selected by an inter-
nal multiplexer under host processor control. The device
accepts industry-standard video levels of 1.23 Volts (sync tip
to peak color = 1 volt sync tip to reference white). Good
channel-to-channel isolation allows active video on all three
inputs simultaneously. Antialiasing filtering (if used) and
line termination resistors must be provided externally. The
input selection is controlled by two bits in the Control Regis-
ter.
Horizontal Phase-Locked Loop
A phase-locked loop generates PXCK, at twice the pixel
rate. The reference signal for the horizontal phase-locked
loop is generated by the Direct Digital Synthesizer (DDS).
The DDS output is constructed with an internal D/A con-
verter and is output from the TMC22071A via the DDS OUT
pin. This signal is passed through an external LC filter and
input to the horizontal phase-comparator.
The frequency of the DDS output is one ninth of that of
PXCK.
A 20 MHz clock is required to drive the DDS. Preferably,
this may be input to the TMC22071A via CMOS levels on
the CLK IN pin. Alternately, a 20 MHz crystal may be
directly connected between CLK IN and CLK OUT with
tuning capacitors to activate the internal crystal oscillator cir-
cuitry.
If incoming video is lost or disconnected after the
TMC22071A has acquired and locked, PXCK, GHSYNC,
Analog Clamp
The front-end analog clamp ensures that the input video falls
within the active range of the A/D converter. The digitized
composite video output can be clamped to the back porch by
a secondary digital clamp.
Automatic Gain Adjustment
Since video signals may vary substantially from nominal lev-
els, the TMC22071A performs an automatic level setting
routine to establish correct signal amplitudes for digitizing.
The TMC22071A relies upon the presence of the sync
tip-to-back porch voltage to determine the gain required for
the input video signal.
Sync tip compression or clipping is often affected by APL
(Average Picture Level) variation. Rather than tracking
minor variations in sync tip amplitude and constantly adjust-
ing video gain, the TMC22071A establishes proper signal
2
PRODUCT SPECIFICATION
TMC22071A
GVSYNC and GRS data will continue. The GRS data will
be the initial subcarrier frequency and phase values selected
by the Format select bits of the Control Register. The
TMC22071A will acquire and lock to incoming video within
two frames after video is restored.
Subcarrier frequency, subcarrier phase, and Field ID data
(GRS) are transmitted in 4-bit nibbles over CVBS
3-0
during
the horizontal sync tip period at the PXCK rate.
Microprocessor Interface
Since microprocessor buses are notoriously noisy from a
wide-band analog point of view, the microprocessor inter-
face bus is only one bit wide, rather than the more customary
eight. The operation of this bus is similar to other bus-
controlled devices except that the TMC22071A internal
Control Register is accessed one bit at a time.
A sequence of 47 bits is written to or read from the LSB of a
standard microprocessor port. Writing to or reading from the
secondary address results in the transfer of data to or from
the internal shift register.
The RESET input, when LOW, sets all internal state
machines to their initialized conditions. Returning the
RESET pin HIGH starts the signal acquisition sequence
which lasts until locking with the gain-adjusted and clamped
video signal is achieved.
Subcarrier Phase-Locked Loop
A fully-digital phase-locked loop is used to extract the phase
and frequency of the incoming color burst. These frequency
and phase values are output over the CVBS bus during the
horizontal sync period. Fairchild’s video decoder and gen-
lockable encoder chips will accept these data directly.
Back Porch Digital Clamp
A digital back-porch clamp is employed to ensure a constant
blanking level. It digitally offsets the data from the A/D con-
verter to set the back porch level to precisely 3C
h
for NTSC
and 40
h
for PAL. When the digital clamp is enabled, the
CVBS video output data is determined from the A/D conver-
sion result minus the back porch level + 3C
h
(40
h
for PAL).
Digitized Video Output
The digitized 8-bit video output is provided over an 8-bit
wide CVBS data port, synchronous with PXCK and LDV.
Pin Assignments
1 68
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Name
V
DD
CVBS
0
CVBS
1
CVBS
2
CVBS
3
CVBS
4
V
DD
D
GND
CVBS
5
CVBS
6
CVBS
7
GHSYNC
GVSYNC
VALID
D
GND
D
GND
LDV
Pin
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Name
V
DD
PXCK
D
GND
D
GND
V
DD
V
DDA
A
GND
V
DDA
V
DDA
A
GND
R
B
V
IN3
V
DDA
V
IN2
A
GND
V
DDA
V
IN1
Pin
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Name
A
GND
R
T
A
GND
V
REF
A
GND
V
DDA
A
GND
C
BYP
PFD IN
A
GND
DDS OUT
PXCK SEL
V
DDA
COMP
A
GND
D
GND
CLK IN
Pin
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Name
V
DD
CLK OUT
EXT PXCK
D
GND
D
GND
D
GND
V
DD
V
DD
A
0
R/W
CS
V
DD
RESET
D
GND
D
0
INT
D
GND
65-22071-02
3
TMC22071A
PRODUCT SPECIFICATION
Pin Assignments
(continued)
80
81
51
50
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16*
17
18
19
20
21
22
23
24
25
Name
A
0
NC
NC
R/W
CS
V
DD
RESET
D
GND
D
0
NC
NC
NC
NC
NC
NC
D
GND
INT
V
DD
NC
NC
CVBS
0
CVBS
1
CVBS
2
CVBS
3
CVBS
4
Pin
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41*
42*
43
44
45
46
47
48
49
50
Name
V
DD
D
GND
CVBS
5
CVBS
6
CVBS
7
NC
GHSYNC
GVSYNC
VALID
NC
NC
NC
D
GND
D
GND
LDV
D
GND
V
DD
NC
V
DD
PXCK
D
GND
D
GND
V
DD
V
DDA
A
GND
Pin
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Name
V
DDA
V
DDA
NC
NC
A
GND
NC
R
B
V
IN3
NC
V
DDA
V
IN2
NC
A
GND
V
DDA
V
IN1
NC
A
GND
R
T
A
GND
V
REF
NC
A
GND
V
DDA
A
GND
C
BYP
Pin
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Name
NC
PFD IN
NC
NC
NC
A
GND
DDS OUT
NC
NC
NC
PXCK SEL
V
DDA
COMP
A
GND
D
GND
CLK IN
V
DD
CLK OUT
EXT PXCK
D
GND
D
GND
D
GND
V
DD
NC
V
DD
65-22071-02B
100
1
30
31
Notes:
1. NC = Do Not Connect.
* These pins are not connected in the
TMC22071A. However, you should
connect these pins as shown for
compatibility with future genlock ICs.
Pin Definitions
Pin Number
Pin Name
Video Input
V
IN1-3
Clocks
CLK IN
51
91
CMOS
20 MHz DDS clock input.
20 MHz CMOS clock input to DDS. This
pin may also be used along with CLK OUT for directly connecting
crystals.
Inverted clock output.
Inverted DDS clock output. This pin may also
be used along with CLK IN for directly connecting a crystal.
2x Pixel clock output.
2x oversampled line-locked clock output.
Pixel clock output.
Delayed pixel clock output. LDV runs at 1/2 the
rate of PXCK and its rising edge is useful for transferring CVBS
digital video from the TMC22071A to the TMC22x9x Digital Video
Encoders.
External PXCK input.
Input for external PXCK clock source.
PXCK source select.
Select input for internal or external PXCK.
When HIGH, the internally generated line-locked PXCK is selected.
When LOW, the external PXCK source is enabled.
34, 31,
29
65, 61,
58
1.23Vp-p
Composite Video Input.
Video inputs,1.25 Volts peak-to-peak, sync
tip to peak color
68 pin
PLCC
100 pin
MQFP
Pin Type
Function
CLK OUT
PXCK
LDV
53
19
17
93
45
40
CMOS
CMOS
CMOS
EXT PXCK
PXCK SEL
54
46
94
86
CMOS
CMOS
4
TMC22071A
PRODUCT SPECIFICATION
Pin Definitions
(continued)
Pin Number
Pin Name
GHSYNC
68 pin
PLCC
12
100 pin
MQFP
32
Pin Type
CMOS
Function
Horizontal sync output.
When the TMC22071A is locked to
incoming video, the GHSYNC pin provides a negative-going pulse
after the falling edge of the horizontal sync pulse. There is a fixed
number of PXCK clock cycles between adjacent falling edges of
GHSYNC, except following a VCR headswitch.
Vertical sync output.
When the TMC22071A is locked to incoming
video, the GVSYNC pin provides a negative-going edge after the
start of the first vertical sync pulse of a vertical blanking interval.
Composite output bus.
8-bit composite video data is output on this
bus at 1/2 the PXCK rate. During horizontal sync, field ID, subcarrier
frequency, and subcarrier phase are available on this bus.
Data l/O port.
Microprocessor data port. All control parameters are
loaded into and read back from the Control Register over this 1-bit
bus.
mP
port control.
Microprocessor address bus. A LOW on this input
loads the l/O Port Shift Register with data from D
0
and CS. A HIGH
transfers the l/O Port Shift Register contents into the Control Register
on the last falling edge of CS.
Chip select.
When CS is HIGH, D
0
is in a high-impedance state and
ignored. When CS is LOW, the microprocessor can read or write D
0
data into the Control Register.
Master reset input.
Bringing RESET LOW forces the internal state
machines to their starting states, loads the Control Register with
default values, and disables outputs. Bringing RESET HIGH restarts
the TMC22071A in its default mode.
Bus read/write control.
When R/W and A
0
are LOW, the
microprocessor can write to the Control Register over D
0
. When R/W
is HIGH and A
0
is LOW, the contents of the Status Register are read
over D
0
.
Interrupt output.
This output is LOW if the internal horizontal phase
lock loop is unlocked with respect to incoming video for 128 or more
lines per field. After lock is established, INT goes HIGH.
HSYNC locked flag.
This output, when HIGH indicates that
incoming horizontal sync has been detected within the
±16
pixel
window in time established by previous sync pulses. When LOW, it
indicates that incoming horizontal sync has not been found within the
expected time frame. VALID will toggle if the time stability of
incoming video is such that sync positioning varies more than
±16
pixels or if occasional horizontal sync pulses are missing.
Digital Video
GVSYNC
13
33
CMOS
CVBS
7-0
11-9, 6-
2
30-28,
25-21
CMOS
mP
l/O
D
0
66
9
TTL
A
0
60
1
TTL
CS
62
5
TTL
RESET
64
7
TTL
R/W
61
4
TTL
INT
67
17
TTL
VALID
14
34
TTL
5
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