PCI Express™ Jitter Attenuator
874005-04
Data Sheet
G
ENERAL
D
ESCRIPTION
The 874005-04 is a high performance Differential-to-LVDS Jitter
Attenuator designed for use in PCI Express systems. In some PCI
Express systems, such as those found in desktop PCs, the PCI
Express clocks are generated from a low bandwidth, high phase noise
PLL frequency synthesizer. In these systems, a jitter attenuator may
be required to attenuate high frequency random and deterministic
jitter components from the PLL synthesizer and from the system
board. The 874005-04 has 2 PLL bandwidth modes: 300kHz and
2MHz. The 300kHz mode will provide maximum jitter attenuation,
but higher PLL tracking skew and spread spectrum modulation
from the motherboard synthesizer may be attenuated. The 2MHz
bandwidth provides the best tracking skew and will pass most
spread profiles. The 874005-04 supports Serdes reference clock
frequencies of 100MHz, 125MHz and 250MHz.
The 874005-04 uses IDT’s 3
rd
Generation FemtoClock
TM
PLL
technology to achive the lowest possible phase noise. The device is
packaged in a 24 Lead TSSOP package, making it ideal for use in
space constrained applications such as PCI Express add-in cards.
F
EATURES
•
Five differential LVDS output pairs
•
One differential clock input
•
Supports 100MHz, 125MHz, and 250MHz Serdes reference
clocks
•
CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
•
Output frequency range: 98MHz - 320MHz
•
Input frequency range: 98MHz - 128MHz
• PCI Express (2.5 Gb/S) and Gen 2 (5 Gb/s) jitter compliant
•
RMS phase jitter @ 100MHz (1.875MHz – 20MHz):
0.88ps (typical)
•
VCO range: 490MHz - 640MHz
•
Cycle-to-cycle jitter: 35ps (maximum) QA = QB = ÷4
•
3.3V operating supply
•
Two bandwidth modes allow the system designer to make jitter
attenuation/tracking skew design trade-offs
•
0°C to 70°C ambient operating temperature
•
Available in lead-free (RoHS 6) package
PLL B
ANDWIDTH
BW_SEL
0 = PLL Bandwidth: ~300kHz (default)
1 = PLL Bandwidth: ~2MHz
B
LOCK
D
IAGRAM
OEA Pullup
F_SELA Pulldown
BW_SEL Pulldown
0 = ~300kHz
1 = ~2MHz
CLK Pulldown
nCLK Pullup
F_SELA
0 ÷5
(default)
1 ÷4
QA0
nQA0
QA1
P
IN
A
SSIGNMENT
nQB2
nQA1
QA1
V
DDO
QA0
nQA0
MR
BW_SEL
V
DDA
F_SELA
V
DD
OEA
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
QB2
V
DDO
QB1
nQB1
QB0
nQB0
F_SELB
OEB
GND
GND
nCLK
CLK
Phase
Detector
VCO
490 - 640MHz
nQA1
QB0
F_SELB
0 ÷2
(default)
1 ÷4
nQB0
QB1
nQB1
QB2
M = ÷5
(fixed)
874005-04
nQB2
F_SELB Pulldown
MR Pulldown
OEB Pullup
24-Lead TSSOP
4.40mm x 7.8mm x 0.925mm package body
G Package
Top View
©2016 Integrated Device Technology, Inc
1
January 26, 2016
874005-04 Data Sheet
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 24
2, 3
4, 23
5, 6
7
8
9
10
11
12
13
14
15, 16
17
18
19, 20
21, 22
Name
nQB2, QB2
nQA1, QA1
V
DDO
QA0, nQA0
MR
BW_SEL
V
DDA
F_SELA
V
DD
OEA
CLK
nCLK
GND
OEB
F_SELB
nQB0, QB0
nQB1, QB1
Type
Output
Output
Power
Output
Input
Input
Power
Input
Power
Input
Input
Input
Power
Input
Input
Output
Output
Pullup
Pulldown
Description
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Output supply pins.
Differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs (Qx) to go low and the inverted outputs (nQx) to
Pulldown
go high. When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
Pulldown PLL bandwidth input. See Table 3B. LVCMOS/LVTTL interface levels.
Analog supply pin.
Frequency select pin for QAx/nQAx outputs. See Table 3C. LVCMOS/LVTTL
interface levels.
Core supply pin.
Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are
active. When LOW, the QAx/nQAx outputs are in a high impedance state.
LVCMOS/LVTTL interface levels. See Table 3A.
Inverting differential clock input.
Power supply ground.
Output enable pin for QB pins. When HIGH, the QBx/nQBx outputs are
Pullup active. When LOW, the QBx/nQBx outputs are in a high impedance state.
LVCMOS/LVTTL interface levels. See Table 3A.
Frequency select pin for QBx/nQBx outputs. See Table 3C. LVCMOS/LVTTL
Pulldown
interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Pulldown Non-inverting differential clock input.
Pullup
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
©2016 Integrated Device Technology, Inc
2
January 26, 2016
874005-04 Data Sheet
T
ABLE
3A. O
UTPUT
E
NABLE
F
UNCTION
T
ABLE
Inputs
OEA/OEB
0
1
QAx/nQAx
High Impedance
Enabled
Outputs
QBx/nQBx
High Impedance
Enabled
T
ABLE
3B. PLL B
ANDWIDTH
C
ONTROL
, f
REF
= 100MH
Z
Inputs
BW_SEL
0
1
PLL Bandwidth
~300kHz (default)
~2MHz
T
ABLE
3C. O
UTPUT
F
REQUENCY FOR
I
NPUT
F
REQUENCY
= 100MH
Z
Inputs
F_SELA
0 (default)
0
1
1
F_SELB
0 (default)
1
0
1
QAx/nQAx
VCO/5, 100MHz
VCO/5, 100MHz
VCO/4, 125MHz
VCO/4, 125MHz
Outputs
QBx/nQBx
VCO/2, 250MHz
VCO/4, 125MHz
VCO/2, 250MHz
VCO/4, 125MHz
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
82.3°C/W (0 mps)
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.10
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
DD
3.465
80
10
75
Units
V
V
V
mA
mA
mA
©2016 Integrated Device Technology, Inc
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January 26, 2016
874005-04 Data Sheet
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input High Current
Input Low Current
CLK
nCLK
CLK
nCLK
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
-5
-150
0.15
GND + 0.5
1.3
V
DD
- 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1, 2
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
T
ABLE
4D. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OD
Δ
V
OD
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
Minimum
247
1.125
Typical
Maximum
454
50
Units
mV
mV
V
mV
V
OS
Δ
V
OS
1.25
1.375
50
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
f
MAX
tjit(θ)
tjit(cc)
tsk(o)
tsk(b)
t
R
/ t
F
odc
Parameter
Output Frequency
RMS Phase Jitter (Random);
NOTE 1
Cycle-to-Cycle Jitter, NOTE 2
Output Skew; NOTE 3
Bank Skew: NOTE 4
Output Rise/Fall Time
Output Duty Cycle
QAx
QBx
20% to 80%
300
48
100MHz, Integration Range:
(1.875MHz – 20MHz)
QA, QB = ÷4
QA = ÷5
Test Conditions
Minimum
98
0.88
35
75
90
15
68
500
52
Typical
Maximum
320
Units
MHz
ps
ps
ps
ps
ps
ps
ps
%
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and frequency, and with equal load conditions.
Measured at the differential cross points.
NOTE 4: Defined as skew within a bank of outputs at the same supply voltage and frequency, and with equal load conditions.
©2016 Integrated Device Technology, Inc
4
January 26, 2016
874005-04 Data Sheet
P
ARAMETER
M
EASUREMENT
I
NFORMATION
3.3V LVDS O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
D
IFFERENTIAL
I
NPUT
L
EVEL
C
YCLE
-
TO
-C
YCLE
J
ITTER
O
UTPUT
S
KEW
B
ANK
S
KEW
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
©2016 Integrated Device Technology, Inc
5
January 26, 2016
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