ADVANCE INFORMATION
CRYSTAL-TO-MLVDS PCI EXPRESS™
CLOCK SYNTHESIZER W/SPREAD SPECTRUM
ICS845204
General Description
The ICS845204 is a 4 output PCI Express clock
synthesizer optimized to generate low jitter PCI
HiPerClockS™
Express™ reference clocks with or without spread
spectrum modulation and is a member of the
HiPerClockS™ family of high performance clock
solutions from IDT. Spread type and amount can be configured via
the SSC control pins. Using a 25MHz, 18pF parallel resonant
crystal, the device will generate M-LVDS clocks at either 25MHz,
100MHz, 125MHz or 250MHz. The ICS845204 uses a low jitter
VCO that easily meets PCI Express jitter requirements and is
packaged in a 32-pin VFQFN package.
Features
•
•
•
•
•
•
•
•
•
•
•
Four differential spread spectrum clock outputs
Each output can be individually disabled by separate
output-enable inputs
Crystal oscillator interface designed for 18pF,
25MHz parallel resonant crystal
Supports the following output frequencies:
25MHz, 100MHz, 125MHz or 250MHz
VCO range: 250MHz - 700MHz
Supports SSC downspread at 0.05% and -0.75%, centerspread
at ±0.25% and no spread options
Cycle-to-cycle jitter: 50ps (maximum) design target
Period jitter, RMS: TBD
Full 3.3V output supply mode
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
ICS
Pin Assignment
GND
V
DDA
OE1
32 31 30 29 28 27 26 25
OE0
V
DD
nQ3
Q3
V
DDO
nc
FSEL0
nc
1
2
3
4
5
6
7
8
9
FSEL1
nQ1
nQ0
Q0
nc
Q1
24
23
22
21
20
19
18
17
10 11 12 13 14 15 16
XTAL_OUT
OE2
SSC0
XTAL_IN
GND
OE3
V
DD
nc
nc
GND
Q2
nQ2
SSC1
nc
GND
ICS845204
32 Lead VFQFN
5mm x 5mm x 0.925mm
package body
K Package
Top View
Block Diagram
00
25MHz
PLL Bypass
Q0
nQ0
XTAL_IN
OSC
XTAL_OUT
Phase
Detector
VCO
250-700MHz
01
10
11
÷5
÷4
÷2
Pullup
OE0
Q1
nQ1
Pullup
OE1
Feedback Divider
÷20
Q2
nQ2
Pullup
OE2
SSC[1:0]
Pullup:Pullup
Default = 100MHz
Pulldown:Pullup
2
Spread Spectrum
Control
Q3
nQ3
Pullup
OE3
2
FSEL[1:0]
The Advance Information presented herein represents a product that is developmental or prototype. The noted characteristics are design targets. Integrated
Device Technologies, Inc. (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™
M-LVDS CLOCK SYNTHESIZER
1
ICS845204AK SEPTEMBER 25, 2007
ICS845204
CRYSTAL-TO-MLVDS CLOCK SYNTHESIZER W/SPREAD SPECTRUM
ADVANCE INFORMATION
Table 1. Pin Descriptions
Number
1
2, 11
3, 4
5
6, 8, 18, 23,
24, 27
7
9
10,
19
12
13,
14
15
16, 17, 22, 30
20, 21
25, 26
28
29
31, 32
Name
OE0
V
DD
nQ3, Q3
V
DDO
nc
FSEL0
FSEL1
SSC0,
SSC1
OE3
XTAL_IN
XTAL_OUT
OE2
GND
nQ2, Q2
nQ1, Q1
V
DDA
OE1
nQ0, Q0
Input
Power
Output
Power
Unused
Input
Input
Input
Input
Input
Input
Power
Output
Output
Power
Input
Output
Pullup
Pullup
Pullup
Pulldown
Pullup
Pullup
Type
Pullup
Description
Output enable pin for Q0/nQ0 outputs. Logic High, outputs are enabled.
Logic LOW, outputs are in Hi-Z. LVCMOS/LVTTL interface levels.
Core supply pins.
Differential output pair. M-LVDS interface levels.
Output supply pin.
No connect.
Output frequency select pins. See Table 3A. LVCMOS/LVTTL interface levels.
Output frequency select pin. See Table 3A. LVCMOS/LVTTL interface levels.
Spread spectrum control pins. See Table 3B. LVCMOS/LVTTL interface levels.
Output enable pin for Q3/nQ3 outputs. Logic High, outputs are enabled.
Logic LOW, outputs are in Hi-Z. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Output enable pin for Q2/nQ2 outputs. Logic High, outputs are enabled.
Logic LOW, outputs are in Hi-Z. LVCMOS/LVTTL interface levels.
Power supply ground.
Differential output pair. M-LVDS interface levels.
Differential output pair. M-LVDS interface levels.
Analog supply pin.
Output enable pin for Q1/nQ1 outputs. Logic High, outputs are enabled.
Logic LOW, outputs are in Hi-Z. LVCMOS/LVTTL interface levels.
Differential output pair. M-LVDS interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
Ω
k
Ω
IDT™ / ICS™
M-LVDS CLOCK SYNTHESIZER
2
ICS845204AK SEPTEMBER 25, 2007
ICS845204
CRYSTAL-TO-MLVDS CLOCK SYNTHESIZER W/SPREAD SPECTRUM
ADVANCE INFORMATION
Function Tables
Table 3A. F_SEL[1:0] Function Table
Inputs
FSEL1
0
0
1
1
FSEL0
0
1
0
1
Outputs
Q[0:3]/nQ[0:3]
PLL Bypass (25MHz)
100MHz (default)
125MHz
250MHz
SSC1
0
0
1
1
Table 3B. SSC[1:0] Function Table
Inputs
SSC0
0
1
0
1
Center ± -0.25
Down -0.5
Down -0.75
No Spread (default)
Spread%
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuos Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
42.4°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Power Supply Current
Test Conditions
Minimum
3.135
V
DD
– I
DDA
*10
Ω
3.135
Typical
3.3
3.3
3.3
TBD
TBD
TBD
Maximum
3.465
V
DD
3.465
Units
V
V
V
mA
mA
mA
IDT™ / ICS™
M-LVDS CLOCK SYNTHESIZER
3
ICS845204AK SEPTEMBER 25, 2007
ICS845204
CRYSTAL-TO-MLVDS CLOCK SYNTHESIZER W/SPREAD SPECTRUM
ADVANCE INFORMATION
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
F_SEL1
Input
High Current
SSC0, SSC1,
FSEL0, OE0:OE3
F_SEL1
I
IL
Input
Low Current
SSC0, SSC1,
FSEL0, OE0:OE3
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
Table 4C. M-LVDS DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
I
SC
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Output Short Circuit Current
0.30
50
43
Test Conditions
Minimum
480
50
2.10
Typical
Maximum
650
Units
mV
mV
V
mV
mA
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
Test Conditions
Minimum
Typical
Fundamental
25
50
7
TBD
MHz
Maximum
Units
Ω
pF
mW
IDT™ / ICS™
M-LVDS CLOCK SYNTHESIZER
4
ICS845204AK SEPTEMBER 25, 2007
ICS845204
CRYSTAL-TO-MLVDS CLOCK SYNTHESIZER W/SPREAD SPECTRUM
ADVANCE INFORMATION
AC Electrical Characteristics
Table 6. AC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°
Parameter Symbol
f
OUT
Output Frequency
25MHz,
Integration Range: 12kHz – 20MHz
100MHz,
Integration Range: 12kHz – 20MHz
125MHz,
Integration Range: 12kHz – 20MHz
250MHz,
Integration Range: 12kHz – 20MHz
25MHz
tjit(cc)
Cycle-to-Cycle Jitter;
NOTE 1, 2
100MHz
125MHz
250MHz
tsk(o)
F
XTAL
F
M
F
MF
SSC
RED
t
STABLE
t
R
/ t
F
odc
Output Skew; NOTE 2, 3
Crystal Input Range: NOTE 1
SSC Modulation Frequency;
NOTE 4
SSC Modulation Factor;
NOTE 4
Spectral Reduction
Power-up Stable Clock
Output
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
TBD
50
TBD
25
TBD
TBD
TBD
10
Test Conditions
Minimum
Typical Maximum
25
100
125
TBD
TBD
TBD
TBD
50
50
50
50
Units
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
ps
ps
MHz
kHz
%
dB
ms
ps
%
tjit(per)
Period Jitter, Random
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Only valid within the VCO operating range.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: Spread Spectrum clocking enabled.
IDT™ / ICS™
M-LVDS CLOCK SYNTHESIZER
5
ICS845204AK SEPTEMBER 25, 2007
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
