Radiation Hardened and SEE Hardened 6A
Synchronous Buck Regulator with Integrated
MOSFETs
ISL70001SRH
The ISL70001SRH is a radiation hardened and SEE
hardened high efficiency monolithic synchronous buck
regulator with integrated MOSFETs. This single chip
power solution operates over an input voltage range
of 3V to 5.5V and provides a tightly regulated output
voltage that is externally adjustable from 0.8V to
~85% of the input voltage. Output load current
capacity is 6A for T
J
< +145°C
.
The ISL70001SRH utilizes peak current-mode control
with integrated compensation and switches at a fixed
frequency of 1MHz. Two ISL70001SRH devices can be
synchronized 180° out-of-phase to reduce input RMS
ripple current. These attributes reduce the number and
size of external components required, while providing
excellent output transient response. The internal
synchronous power switches are optimized for high
efficiency and good thermal performance.
The chip features a comparator type enable input that
provides flexibility. It can be used for simple digital
on/off control or, alternately, can provide
undervoltage lockout capability by precisely sensing
the level of an external supply voltage using two
external resistors. A power-good signal indicates
when the output voltage is within ±11% typical of the
nominal output voltage.
Regulator start-up is controlled by an analog soft-start
circuit, which can be adjusted from approximately 2ms
to 200ms using an external capacitor.
The ISL70001SRH incorporates fault protection for
the regulator. The protection circuits include input
undervoltage, output undervoltage and output
overcurrent.
High integration makes the ISL70001SRH an ideal
choice to power many of today’s small form factor
applications. Two devices can be synchronized to
provide a complete power solution for large scale
digital ICs, like field programmable gate arrays
(FPGAs), that require separate core and I/O voltages.
Specifications for Rad Hard QML devices are
controlled by the Defense Supply Center in
Columbus (DSCC). The SMD numbers listed in the
Ordering Information Table on page 2 must be
used when ordering.
Detailed Electrical Specifications for these
devices are contained in SMD 5962-09225. A link
is provided on our website for downloading.
ISL70001SRH
Features
• Electrically Screened to DSCC SMD 5962-09225
• QML Qualified per MIL-PRF-38535 Requirements
• Full Mil-Temp Range Operation (T
A
= -55°C to
+125°C)
• Radiation Hardness
- Total Dose [50-300rad(Si)/s] . . . 100krad(Si) min
• SEE Hardness
- SEL and SEB LET
eff
. . . . . . 86.4MeV/mg/cm
2
min
- SEFI X-section (LET
eff
= 86.4MeV/mg/cm
2
)
1.4 x 10
-6
cm
2
max
- SET LET
eff
(< 1 Pulse Perturbation)
86.4MeV/mg/cm
2
min
• High Efficiency > 90%
• Fixed 1MHz Operating Frequency
• Operates from 3V to 5.5V Supply
• ±1% Reference Voltage over Line, Load,
Temperature and Radiation
• Adjustable Output Voltage
- Two External Resistors Set V
OUT
from 0.8V to
~85% of V
IN
• Excellent Dynamic Response
• Bi-directional SYNC Pin Allows Two Devices to be
Synchronized 180
°
Out-of-Phase
• Device Enable with Comparator Type Input
• Power-Good Output Voltage Monitor
• Adjustable Analog Soft-Start
• Input Undervoltage, Output Undervoltage and
Output Overcurrent Protection
• Starts Into Pre-Biased Load
Applications*
(see page 16)
• FPGA, CPLD, DSP, CPU Core or I/O Voltages
• Low-Voltage, High-Density Distributed Power
Systems
December 15, 2009
FN6947.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL70001SRH
Functional Block Diagram
AVDD
AGND
DVDD
DGND
EN
PORSEL
POWER-ON
RESET (POR)
PVINx
CURRENT
SENSE
SS
SOFT
START
SLOPE
COMPENSATION
PWM
CONTROL
LOGIC
FB
EA
GM
GATE
DRIVE
LXx
COMPENSATION
PGNDx
PGOOD
UV
POWER-GOOD
REF
PWM
REFERENCE
0.6V
BIT
TDI
TDO
TRIM
SYNC
M/S
ZAP
Ordering Information
ORDERING NUMBER
5962R0922501QXC
5962R0922501VXC
5962R0922501V9A
ISL70001SRHF/PROTO
ISL70001SRHX/SAMPLE
NOTE:
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant
and compatible with both SnPb and Pb-free soldering operations.
2. For Moisture Sensitivity Level (MSL), please see device information page for
ISL70001SRH.
For more information on MSL
please see techbrief
TB363.
PART NUMBER
(Note 2)
ISL70001SRHQF (Note 1)
ISL70001SRHVF (Note 1)
ISL70001SRHVX
ISL70001SRHF/PROTO (Note 1)
ISL70001SRHX/SAMPLE
TEMP. RANGE
(°C)
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
PACKAGE
48 Ld CQFP (Pb-Free)
48 Ld CQFP (Pb-Free)
Die
48 Ld CQFP (Pb-Free)
Die
2
FN6947.0
December 15, 2009
ISL70001SRH
Pin Configuration
ISL70001SRH
(48 LD CQFP)
TOP VIEW
PGND2
PGND2
LX1
PGND1
PGND1
PVIN1
PVIN1
PVIN2
PVIN2
PVIN3
SYNC
LX2
M/S
ZAP
TDI
TDO
PGOOD
SS
DVDD
DVDD
DGND
DGND
AGND
AGND
7
8
9
10
11
12
13
14
15
16
6 5 4 3 2 1 48 47 46 45 4443
42
41
40
39
38
37
36
35
34
33
PVIN3
LX3
PGND3
PGND3
PGND4
PGND4
LX4
PVIN4
PVIN4
PVIN5
PVIN5
LX5
32
17
31
18
19 20 21 22 23 24 25 26 27 28 29 30
PVIN6
PVIN6
LX6
FB
EN
PORSEL
PGND6
PGND6
PGND5
Pin Descriptions
PIN NUMBER
1, 2, 27, 28, 29,
30, 37, 38, 39,
40, 47, 48
3, 26, 31, 36,
41, 46
PIN NAME
PGNDx
DESCRIPTION
These pins are the power grounds associated with the corresponding internal power blocks.
Connect these pins directly to the ground plane. These pins should also connect to the
negative terminals of the input and output capacitors. Locate the input and output capacitors
as close as possible to the IC.
These pins are the outputs of the corresponding internal power blocks and should be
connected to the output filter inductor. Internally, these pins are connected to the synchronous
MOSFET power switches. To minimize voltage undershoot, it is recommended that a Schottky
diode be connected from these pins to PGNDx. The Schottky diode should be located as close
as possible to the IC.
These pins are the power supply inputs to the corresponding internal power blocks. These pins
must be connected to a common power supply rail, which must fall in the range of 3V to 5.5V.
Bypass these pins directly to PGNDx with ceramic capacitors located as close as possible to
the IC.
This pin is the synchronization I/O for the IC. When configured as an output (Master Mode),
this pin drives the SYNC input of another ISL70001SRH. When configured as an input (Slave
Mode), this pin accepts the SYNC output from another ISL70001SRH or an external clock.
Synchronization of the slave unit is 180° out-of-phase with respect to the master unit. If
synchronizing to an external clock, the clock must be SEE hardened and the frequency must
be within the range of 1MHz ±20%.
This pin is the Master/Slave input for selecting the direction of the bi-directional SYNC pin. For
SYNC = Output (Master Mode), connect this pin to DVDD. For SYNC = Input (Slave Mode),
connect this pin to DGND.
This pin is a trim input and is used to adjust various internal circuitry. Connect this pin to
DGND.
This pin is the test data input of the internal BIT circuitry. Connect this pin to DGND.
This pin is the test data output of the internal BIT circuitry. Connect this pin to DGND.
LXx
4, 5, 24, 25, 32,
33, 34, 35, 42,
43, 44, 45
6
PVINx
SYNC
7
M/S
8
9
10
ZAP
TDI
TDO
3
PGND5
AVDD
REF
FN6947.0
December 15, 2009
ISL70001SRH
Pin Descriptions
(Continued)
PIN NUMBER
11
PIN NAME
PGOOD
DESCRIPTION
This pin is the power-good output. This pin is an open drain logic output that is pulled to DGND
when the output voltage is outside a ±11% typical regulation window. This pin can be pulled
up to any voltage from 0V to 5.5V, independent of the supply voltage. A nominal 1kΩ to 10kΩ
pull-up resistor is recommended. Bypass this pin to DGND with a 10nF ceramic capacitor to
mitigate SEE.
This pin is the soft-start input. Connect a ceramic capacitor from this pin to DGND to set the
soft-start output ramp time in accordance with Equation 1:
t
SS
=
C
SS
⋅
V
REF
⁄
I
SS
(EQ. 1)
12
SS
Where:
t
SS
= Soft-start output ramp time
C
SS
= Soft-start capacitor
V
REF
= Reference voltage (0.6V typical)
I
SS
= Soft-start charging current (23µA typical)
Soft-start time is adjustable from approximately 2ms to 200ms.
The range of the soft-start capacitor should be 82nF to 8.2µF, inclusive.
13, 14
DVDD
These pins are the bias supply inputs to the internal digital control circuitry. Connect these
pins together at the IC and locally filter them to DGND using a 1Ω resistor and a 1µF ceramic
capacitor. Locate both filter components as close as possible to the IC.
These pins are the digital ground associated with the internal digital control circuitry. Connect
these pins directly to the ground plane.
These pins are the analog ground associated with the internal analog control circuitry. Connect
these pins directly to the ground plane.
This pin is the bias supply input to the internal analog control circuitry. Locally filter this pin
to AGND using a 1Ω resistor and a 1µF ceramic capacitor. Locate both filter components as
close as possible to the IC.
This pin is the internal reference voltage output. Bypass this pin to AGND with a 220nF ceramic
capacitor located as close as possible to the IC. The bypass capacitor is needed to mitigate
SEE. No current (sourcing or sinking) is available from this pin.
This pin is the voltage feedback input to the internal error amplifier. Connect a resistor from
FB to VOUT and from FB to AGND to adjust the output voltage in accordance with Equation 2:
V
OUT
=
V
REF
⋅ [
1
+
(
R
T
⁄
R
B
) ]
(EQ. 2)
15, 16
17, 18
19
DGND
AGND
AVDD
20
REF
21
FB
Where:
V
OUT
= Output voltage
V
REF
= Reference voltage (0.6V typical)
R
T
= Top divider resistor (Must be 1kΩ)
R
B
= Bottom divider resistor
The top divider resistor must be 1kΩ to mitigate SEE. Connect a 4.7nF ceramic capacitor across
RT to mitigate SEE and to improve stability margins.
22
EN
This pin is the enable input to the IC. This is a comparator type input with a rising threshold
of 0.6V and programmable hysteresis. Driving this pin above 0.6V enables the IC. Bypass this
pin to AGND with a 10nF ceramic capacitor to mitigate SEE.
This pin is the input for selecting the rising and falling POR (Power-On-Reset) thresholds. For
a nominal 5V supply, connect this pin to DVDD. For a nominal 3.3V supply, connect this pin to
DGND. For nominal supply voltages between 5V and 3.3V, connect this pin to DGND.
23
PORSEL
4
FN6947.0
December 15, 2009
ISL70001SRH
Typical Application Schematic
PVIN1
5V
PVIN2
100µF
1µF
PVIN3
LX3
LX2
LX1
PVIN4
LX4
PVIN5
1µF
PVIN6
LX5
1µH
LX6
20V
3A
FB
470µF
1kΩ
4.7nF
1.8V
6A
1
DVDD
1µF
DGND
ISL70001SRH
0V TO 5.5V
499Ω
1
AVDD
1µF
AGND
PGOOD
10nF
VSENSE
SYNC
EN
10nF
REF
220nF
M/S
PORSEL
TDI
TDO
ZAP
SS
100nF
PGND4
PGND1
FIGURE 1. 5V INPUT SUPPLY VOLTAGE WITH MASTER MODE SYNCHRONIZATION
5
PGND2
PGND3
PGND5
PGND6
FN6947.0
December 15, 2009
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