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L-FW32307T128-DT

产品描述L-FW32307T128-DT
产品类别嵌入式处理器和控制器    微控制器和处理器   
文件大小501KB,共2页
制造商AVAGO
官网地址http://www.avagotech.com/
下载文档 详细参数 选型对比 全文预览

L-FW32307T128-DT概述

L-FW32307T128-DT

L-FW32307T128-DT规格参数

参数名称属性值
厂商名称AVAGO
包装说明,
Reach Compliance Codecompliant

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FW323 07 T128/NV129
1394a PCI PHY/Link Open Host Controller Interface
Product Brief
Features
1394a-2000 OHCI link and PHY core function in a sin-
gle device:
— Single-chip link and PHY enable smaller, simpler,
more efficient motherboard and add-in card
designs.
— Enables lower system costs.
— Compatibility with current
Microsoft Windows
®
driv-
ers and common applications.
— Supports low-power system designs (CMOS imple-
mentation, power management features).
— Provides LPS, LKON, and CNA outputs to support
legacy power management implementations.
OHCI:
— Complies with the 1394
OHCI 1.1 Specification.
— OHCI 1.0 backwards compatible—configurable via
EEPROM to operate in either OHCI 1.0 or OHCI 1.1
mode.
— Listed on
Windows
hardware compatibility list
http://testedproducts.windowsmarketplace.com/.
— Compatible with
Microsoft Windows
and
MacOS
®
operating systems.
— 4 Kbyte isochronous transmit FIFO.
— 2 Kbyte asynchronous transmit FIFO.
— 4 Kbyte isochronous receive FIFO.
— 2 Kbyte asynchronous receive FIFO.
— Dedicated asynchronous and isochronous descrip-
tor-based DMA engines.
— Eight isochronous transmit/receive contexts.
— Prefetches isochronous transmit data.
— Supports posted write transactions.
— Supports parallel processing of incoming physical
read and write requests.
— May be used without an EEPROM when the system
BIOS is programmed with the EEPROM contents.
1394a-2000 PHY core:
— Compliant with
IEEE
®
1394a-2000, Standard for a
High Performance Serial Bus
(Supplement).
— Provides three fully compliant cable ports, each
supporting 400 Mbits/s, 200 Mbits/s, and
100 Mbits/s traffic.
— Does not require external filter capacitor for PLL.
— Supports link-on as a part of the internal PHY core-
link interface.
— Supports arbitrated short bus reset to improve
utilization of the bus.
— Supports multispeed packet concatenation.
Product Brief
— Supports PHY pinging and remote PHY access
packets.
— Reports cable power fail interrupt when voltage at
CPS pin falls below 7.5 V.
PCI:
— Revision 2.3 compliant.
— 33 MHz/32-bit operation.
— Programmable burst size thresholds for PCI data
transfer.
— Supports optimized memory read line, memory read
multiple, and memory write invalidate burst com-
mands.
— Supports CLKRUN# protocol per PCI Mobile Design
Guide.
— Supports
Mini PCI
®
Specification v1.0, including
Mini PCI
power requirements.
— CardBus support per PC Card Standard
Release 8.0, including 128 bytes of on-chip tuple
memory.
— Supports
PCI Bus Power Management Interface
Specification
v.1.1, including D3cold wake-ups.
— I
2
C serial ROM interface.
CMOS process.
3.3 V operation, 5 V tolerant inputs.
128-pin TQFP or 129-ball VTFSBGA package.
NAND tree test mode.
August 2006
www.agere.com

L-FW32307T128-DT相似产品对比

L-FW32307T128-DT L-FW32307T128-DB
描述 L-FW32307T128-DT L-FW32307T128-DB
厂商名称 AVAGO AVAGO
Reach Compliance Code compliant compliant

 
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