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CY7C346
128-Macrocell MAX
®
EPLD
Features
• 128 macrocells in eight logic array blocks (LABs)
• 20 dedicated inputs, up to 64 bidirectional I/O pins
• Programmable interconnect array
• 0.8-micron double-metal CMOS EPROM technology
• Available in 84-pin CLCC, PLCC, and 100-pin PGA,
PQFP
The 128 macrocells in the CY7C346 are divided into eight
LABs, 16 per LAB. There are 256 expander product terms, 32
per LAB, to be used and shared by the macrocells within each
LAB.
Each LAB is interconnected through the programmable inter-
connect array, allowing all signals to be routed throughout the
chip.
The speed and density of the CY7C346 allow it to be used in
a wide range of applications, from replacement of large
amounts of 7400-series TTL logic, to complex controllers and
multifunction chips. With greater than 25 times the functionality
of 20-pin PLDs, the CY7C346 allows the replacement of over
50 TTL devices. By replacing large amounts of logic, the
CY7C346 reduces board space, part count, and increases
system reliability.
Functional Description
The CY7C346 is an Erasable Programmable Logic Device
(EPLD) in which CMOS EPROM cells are used to configure
logic functions within the device. The MAX
®
architecture is
100% user-configurable, allowing the device to accommodate
a variety of independent logic functions.
Logic Block Diagram
.. 1
. 78
. 79
80
. 83
. 84
.. 2
.. 5
.. 6
.. 7
(C7) [16]
(A10) [9]
(B9) [10]
(A9) [11]
(A8) [14]
(B7) [15]
(A7) [17]
(C6) [20]
(A5) [21]
(B5) [22]
. INPUT/CLK
.....
INPUT
.....
INPUT
.....
INPUT
INPUT
.....
.....
INPUT
.....
INPUT
INPUT
.....
INPUT
.....
.....
INPUT
SYSTEM CLOCK
LAB A
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
LAB H
MACROCELL 120
MACROCELL 119
MACROCELL 118
MACROCELL 117
MACROCELL 116
MACROCELL 115
MACROCELL 114
MACROCELL 113
MACROCELL 121–128
LAB G
MACROCELL 104
MACROCELL 103
MACROCELL 102
MACROCELL 101
MACROCELL 100
MACROCELL 99
MACROCELL 98
MACROCELL 97
P
I
A
MACROCELL 105–112
LAB F
MACROCELL 88
MACROCELL 87
MACROCELL 86
MACROCELL 85
MACROCELL 84
MACROCELL 83
MACROCELL 82
MACROCELL 81
MACROCELL 86–96
LAB E
49
50
51
52
53
54
55
56
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
72
71
70
69
68
67
66
65
[58]
[57]
[56]
[55]
[54]
[53]
[52]
[51]
(M4) NC
(N3) NC
(M3) 55
(N2) 54
(M2) 53
(N1) 52
(L2) 51
(M1) 50
INPUT [59]
INPUT [60]
INPUT [61]
INPUT [64]
INPUT [65]
INPUT [66]
INPUT [67]
INPUT [70]
INPUT [71]
INPUT [72]
(N4)
(M5)
(N5)
(N6)
(M7)
(L7)
(N7)
(L8)
(N9)
(M9)
.
.
.
.
.
.
.
.
.
.
36
37
38
41
42
43
44
47
48
49
8 (B13) [1]
9 (C12) [2]
10 (A13) [3]
11 (B12) [4]
12 (A12) [5]
13 (11) [6]
NC (A11) [7]
NC (B10) [8]
1
2
3
4
5
6
7
8
[100] (C13) NC
[99] (D12) NC
[98] (D13) 77
[97] (E12) 76
[96] (E13) 75
[95] (F11) 74
[92] (G13) 73
[91] (G11) 72
MACROCELL 9–16
LAB B
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
14 (A4)
15 (B4)
16 (A3)
17 (A2)
18 (B3)
21 (A1)
NC (B2)
NC (B1)
[23]
[24]
[25]
[26]
[27]
[28]
[29]
[30]
17
18
19
20
21
22
23
24
[90]
[89]
[86]
[85]
[84]
[83]
[82]
[81]
(G12) NC
(H13) NC
(J13) 71
(J12) 70
(K13) 69
(K12) 68
(L13) 67
(L12) 64
MACROCELL 25–32
LAB C
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
22 (C2) [31]
25 (C1) [32]
26 (D2) [33]
27 (D1) [34]
28 (E2) [35]
29 (E1) [36]
NC (F1) [39]
NC (G2) [40]
33
34
35
36
37
38
39
40
[80]
[79]
[78]
[77]
[76]
[75]
[74]
[73]
(M13)
(M12)
(N13)
(M11)
(N12)
(N11)
(M10)
(N10)
NC
NC
63
60
59
58
57
56
MACROCELL 41–48
LAB D
30 (G3) [41]
31 (G1) [42]
32 (H3) [45]
33 (J1) [46]
34 (J2) [47]
35 (K1) [48]
NC (K2) [49]
NC (L1) [50]
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL 57– 64
3, 20, 37, 54 (A6,B6,F12,F13,H1,H2,M8,N8)
16, 33, 50, 67 (B8,C8,F2,F3,H11,H12,L6,M6)
[18, 19, 43, 44, 68, 69, 93, 94]
[12, 13, 37, 38, 62, 63, 87, 88]
VCC
GND
MACROCELL 73– 80
() – PERTAIN TO 100-PIN PGA PACKAGE
[ ] –PERTAIN TO 100-PIN PQFP PACKAGE
Cypress Semiconductor Corporation
Document #: 38-03005 Rev. *B
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised April 19, 2004
USE ULTRA37000
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FOR
ALL NEW DESIGNS
Selection Guide
7C346-25
Maximum Access Time
Maximum Operating Current
Commercial
Military
Industrial
Maximum Standby Current
Commercial
Military
Industrial
25
250
325
320
225
275
275
7C346-30
30
250
320
320
225
275
275
7C346-35
35
250
320
320
225
275
275
CY7C346
Unit
ns
mA
mA
Pin Configurations
PLCC/CLCC
Top View
INPUT/CLK
INPUT
INPUT
INPUT
V
CC
V
CC
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
GND
GND
PGA
Bottom View
I/O
I/O
I/O
I/O
I/O
I/O
I/O
11 10 9 8 7 6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
I/O
I/O
V
CC
V
CC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
74
73
72
71
70
69
68
67
66
65
64
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
V
CC
V
CC
I/O
I/O
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N
M
L
K
J
H
G
F
E
D
C
B
A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INP
I/O
INP INP INP V
CC
INP
INP GND INP V
CC
INP
GND INP
INP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
V
CC
I/O
I/O
I/O
I/O
I/O
13
V
CC
V
CC
I/O
I/O
I/O
I/O
GND GND
CY7C346
I/O
I/O
I/O
V
CC
I/O
I/O
CY7C346
63
62
61
60
59
58
57
56
55
I/O GND GND
I/O
I/O
I/O
I/O
I/O
1
I/O
I/O
I/O
I/O
I/O
2
I/O
I/O
3
I/O
I/O
4
INP
INP
GND
/CLK
I/O
I/O
I/O
I/O
11
I/O
I/O
12
INP V
CC
INP GND INP
INP V
CC
INP
5
6
7
54
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
INPUT
GND
GND
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
V
CC
V
CC
INPUT
INPUT
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INP INP INP
8
9
10
Document #: 38-03005 Rev. *B
Page 2 of 21
USE ULTRA37000
TM
FOR
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Pin Configurations
(continued)
PQFP
Top View
GND
VCC
GND
CC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
V
I/O
I/O
CY7C346
100 99 98 97 96 95 94 93 92 91 90 89 88
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
INPUT
INPUT
GND
GND
INPUT
INPUT
INPUT/CLK
INPUT
V
CC
V
CC
INPUT
INPUT
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
87 86 85 84 83
82 81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
INPUT
INPUT
V
CC
V
CC
INPUT
INPUT
INPUT
INPUT
GND
GND
INPUT
INPUT
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CY7C346
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Document #: 38-03005 Rev. *B
VCC
VCC
I/O
I/O
Page 3 of 21
USE ULTRA37000
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Logic Array Blocks
There are eight logic array blocks in the CY7C346. Each LAB
consists of a macrocell array containing 16 macrocells, an
expander product term array containing 32 expanders, and an
I/O block. The LAB is fed by the programmable interconnect
array and the dedicated input bus. All macrocell feedbacks go
to the macrocell array, the expander array, and the program-
mable interconnect array. Expanders feed themselves and the
macrocell array. All I/O feedbacks go to the programmable
interconnect array so that they may be accessed by macro-
cells in other LABs as well as the macrocells in the LAB in
which they are situated.
Externally, the CY7C346 provides 20 dedicated inputs, one of
which may be used as a system clock. There are 64 I/O pins
CY7C346
that may be individually configured for input, output, or bidirec-
tional data flow.
Programmable Interconnect Array
The Programmable Interconnect Array (PIA) solves inter-
connect limitations by routing only the signals needed by each
logic array block. The inputs to the PIA are the outputs of every
macrocell within the device and the I/O pin feedback of every
pin on the device.
Timing Delays
Timing delays within the CY7C346 may be easily determined
using
Warp
®
,
Warp
Professional™, or
Warp
Enterprise™
software. The CY7C346 has fixed internal delays, allowing the
user to determine the worst case timing delays for any design.
EXPANDER
DELAY
t
EXP
LOGIC ARRAY
CONTROL DELAY t
CLR
t
LAC
t
PRE
INPUT
DELAY
t
IN
LOGIC ARRAY
DELAY
t
LAD
t
RSU
t
RH
REGISTER
OUTPUT
DELAY
OUTPUT
t
RD
t
OD
t
XZ
t
ZX
INPUT
t
COMB
t
LATCH
SYSTEM CLOCK DELAY t
ICS
CLOCK
DELAY
t
IC
FEEDBACK
DELAY
t
FD
PIA
DELAY
t
PIA
I/O DELAY
t
IO
Figure 1. CY7C346 Internal Timing Model
Design Recommendations
Operation of the devices described herein with conditions
above those listed under “Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this data sheet is not implied. Exposure to absolute maximum
ratings conditions for extended periods of time may affect
device reliability. The CY7C346 contains circuitry to protect
device pins from high static voltages or electric fields, but
normal precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages.
For proper operation, input and output pins must be
constrained to the range GND
≤
(V
IN
or V
OUT
)
≤
V
CC
. Unused
inputs must always be tied to an appropriate logic level
Document #: 38-03005 Rev. *B
(either V
CC
or GND). Each set of V
CC
and GND pins must
be connected together directly at the device. Power supply
decoupling capacitors of at least 0.2
µF
must be connected
between V
CC
and GND. For the most effective decoupling,
each V
CC
pin should be separately decoupled to GND
directly at the device. Decoupling capacitors should have
good frequency response, such as monolithic ceramic types
have.
Design Security
The CY7C346 contains a programmable design security
feature that controls the access to the data programmed into
the device. If this programmable feature is used, a proprietary
design implemented in the device cannot be copied or
retrieved. This enables a high level of design control to be
Page 4 of 21
USE ULTRA37000
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FOR
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obtained since programmed data within EPROM cells is
invisible. The bit that controls this function, along with all other
program data, may be reset simply by erasing the entire
device.
The CY7C346 is fully functionally tested and guaranteed
through complete testing of each programmable EPROM bit
and all internal logic elements thus ensuring 100%
programming yield.
The erasable nature of these devices allows test programs to
be used and erased during early stages of the production flow.
The devices also contain on-board logic test circuitry to allow
verification of function and AC specification once encapsu-
lated in non-windowed packages.
CY7C346
Timing Considerations
Unless otherwise stated, propagation delays do not include
expanders. When using expanders, add the maximum
expander delay t
EXP
to the overall delay. Similarly, there is an
additional t
PIA
delay for an input from an I/O pin when
compared to a signal from straight input pin.
When calculating synchronous frequencies, use t
S1
if all
inputs are on dedicated input pins. The parameter t
S2
should
be used if data is applied at an I/O pin. If t
S2
is greater than
t
CO1
, 1/t
S2
becomes the limiting frequency in the data path
mode unless 1/(t
WH
+ t
WL
) is less than 1/t
S2
.
When expander logic is used in the data path, add the appro-
priate maximum expander delay, t
EXP
to t
S1
. Determine which
of 1/(t
WH
+ t
WL
), 1/t
CO1
, or 1/(t
EXP
+ t
S1
) is the lowest
frequency. The lowest of these frequencies is the maximum
data path frequency for the synchronous configuration.
When calculating external asynchronous frequencies, use
t
AS1
if all inputs are on the dedicated input pins. If any data
is applied to an I/O pin, t
AS2
must be used as the required
set-up time. If (t
AS2
+ t
AH
) is greater than t
ACO1
, 1/(t
AS2
+ t
AH
)
becomes the limiting frequency in the data path mode unless
1/(t
AWH
+ t
AWL
) is less than 1/(t
AS2
+ t
AH
).
When expander logic is used in the data path, add the appro-
priate maximum expander delay, t
EXP
to t
AS1
. Determine
which of 1/(t
AWH
+ t
AWL
), 1/t
ACO1
, or 1/(t
EXP
+ t
AS1
) is the
lowest frequency. The lowest of these frequencies is the
maximum data path frequency for the asynchronous config-
uration.
Typical I
CC
vs. f
MAX
400
I
CC
ACTIVE (mA) Typ.
300
V
CC
= 5.0V
Room Temp.
200
100
0
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz 10 MHz
50 MHz
MAXIMUM FREQUENCY
Output Drive Current
I
O
OUTPUT CURRENT (mA) TYPICAL
The parameter t
OH
indicates the system compatibility of this
device when driving other synchronous logic with positive
input hold times, which is controlled by the same
synchronous clock. If t
OH
is greater than the minimum
required input hold time of the subsequent synchronous
logic, then the devices are guaranteed to function properly
with a common synchronous clock under worst-case
environmental and supply voltage conditions.
The parameter t
AOH
indicates the system compatibility of this
device when driving subsequent registered logic with a
positive hold time and using the same asynchronous clock
as the CY7C346.
In general, if t
AOH
is greater than the minimum required input
hold time of the subsequent logic (synchronous or
asynchronous) then the devices are guaranteed to function
properly under worst-case environmental and supply voltage
conditions, provided the clock signal source is the same.
This also applies if expander logic is used in the clock signal
path of the driving device, but not for the driven device. This
is due to the expander logic in the second device’s clock
signal path adding an additional delay (t
EXP
) causing the
output data from the preceding device to change prior to the
arrival of the clock signal at the following device’s register.
100
I
OL
80
60
40
I
OH
20
V
CC
= 5.0V
Room Temp.
0
0.45
1
2
3
4
5
V
O
OUTPUT VOLTAGE (V)
Document #: 38-03005 Rev. *B
Page 5 of 21
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