ports and timer/counters on a chip. The 47C101/201 are the
standard type devices in the TLCS-47E series.
Part No.
TMP47C101P
TMP47C101M
TMP47C201P
TMP47C201M
ROM
1024 x 8-bit
RAM
64 x 4-bit
Package
DIP16
SOP16
DIP16
SOP16
OTP
TMP47P201VP
T.B.D.
TMP47P201VP
T.B.D.
Piggyback + Adapter
TMP47C990E
+ BM1160 (for DIP)
2048 x 8-bit
128 x 4-bit
Features
• 4-bit single chip microcomputer
• Instruction execution time: 1.3
µ
s (at 6MHz)
• Low voltage operation: 2.2V (at 2MHz RC)
• 89 basic instructions
- Instruction set is the same as TLCS-47 series
• ROM table look-up instructions
• Subroutine nesting: 15 levels max.
• 5 interrupt sources (External: 2, Internal: 3)
- All sources have independent latches each, and multiple
interrupt control is available
• I/O port (11 pins)
• 12-bit Timer/Counters (TC2)
- Timer, event counter, and pulse width measurement
mode
• 12-bit programmable Timer (TC1)
• Interval Timer
• High current outputs
- LED direct drive capability: typ. 20mA x 4 bits (Port R4)
• Hold function
- Battery/Capacitor back-up
• Real Time Emulator: BM4721A + BM1160 (for DIP)
The information contained here is subject to change without notice.
The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties
which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic
equipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equip-
ments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traffic signal, combustion control, all types
of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA.
TOSHIBA CORPORATION
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TMP47C101/201
Pin Assignment (Top View)
Pin Function
Pin Name
R43 to R40
R53 to R50
R81 (T2)
R80 (INT2)
XIN
XOUT
RESET
HOLD (INT1)
VDD
VSS
I/O (Input)
Input
Output
Input
I/O (Input)
Power Supply
I/O
Input/Output
Functions
4-bit I/O port with latch.
When used as input port, the latch must be set to “1”.
Every bit data is possible to be set, cleared and tested by the bit manipulation
instruction of the L-register indirect addressing.
2-bit I/O port with latch.
When used as input port, external interrupt pin, or timer/counter
external input pin, the latch must be set to “1”.
Resonator connecting pins,
For inputting external clock, XIN is used and XOUT is opened.
Reset signal input
Hold request/release signal input
+5 V
OV (GND)
External interrupt 1 input and R82 I/O
Timer/Counter 2 external input
External interrupt 2 input
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TOSHIBA CORPORATION
TMP47C101/201
Operational Description
Concerning the above component parts, the configuration and
functions of hardwares are described.
1. System Configuration
Internal CPU Function
•
•
•
•
2.1 Program Counter (PC)
2.2 Program Memory (ROM)
2.3 H Register, L Register
2.4 Data Memory (RAM)
- Stack
- Stack Pointer Word (SPW)
- Data Counter (DC)
•
•
•
•
•
2.5 ALU, Accumulator
2.6 Flags
2.7 System Controller
2.8 Interrupt Controller
2.9 Reset Circuit
Peripheral Hardware Function
• 3.1 I/O Ports
• 3.2 Interval Timer
• 3.3 Timer/Counters (TC1, TC2)
TOSHIBA CORPORATION
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TMP47C101/201
2. Internal CPU Function
2.1 Program Counter (PC)
The program counter is a 11-bit binary counter which indicates
the address of the program memory storing the next instruc-
tion to be executed.Normally, the PC is incremented by the
number of bytes of the instruction every time it is fetched.
When a branch instruction or a subroutine instruction has been
executed or an interrupt has been accepted, the specified val-
ues listed in Table 2-1 are set to the PC. The PC is initialized to
“0” during reset.
Figure 2-1. Configuration of Program Counter
The PC can directly address a 2048-byte address space.
However, with the short branch, the following points must be
considered:
• Short branch instruction [BSS a]
In [BSS a] instruction execution, when the branch con-
dition is satisfied, the value specified in the instruction
is set to the lower 6 bits of the PC.That is, [BSS a]
becomes the in-page branch instruction. When [BSS
a] is stored at the last address of the page, the upper 5
bits of the PC point the next page, so that branch is
made to the next page.
Table 2-1 Status Change of Program Counter
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TOSHIBA CORPORATION
TMP47C101/201
2.2 Program Memory (ROM)
Programs and fixed data are stored in the program memory.
The instruction to be executed next is read from the address
indicated by the contents of the PC.
The fixed data can be read by using the table look-up in-
structions.
• Table look-up instructions
[LDL A, @DC], [LDH A, @DC+]
The table look-up instructions read the lower and
upper 4 bits of the fixed data stored at the address
specified in the data counter (DC) to place them into
the accumulator. [LDL A, @DC] instruction reads the
lower 4 bits of fixed data, and [LDH A, @DC+] instruc-
tion reads the upper 4 bits.
The DC is a 12-bit register, allowing it to address the
entire program memory space.
Example: When [LDL A, @DC] instruction is executed
with the DC value being 7AO
H
being 58
H
,
“8” is stored in the accumulator; when [LDH
A, @DC+] instruction is executed, “5” is
stored in the accumulator and the DC value
is incremented to 7A1
H
.
Figure 2-2. Configuration of Program Memory
2.2.1 Program Memory Capacity
The 47C101 has 1024 x 8 bits (addresses 000
H
through 3FF
H
)
of program memory (mask ROM), the 47C201 has 2048 x 8
bits (addresses 000
H
through 7FF
H
).
2.2.2 Program Memory Map
Figure 2-3 shows the program memory map. Address 000
H
-
086
H
of the program memory are also used for special pur-
poses. On the 47C101, no physical program memory exists in
the address range 400
H
through 7FF
H
. However, if this space
is accessed by program, the most significant bit of each
address is always regarded as “0” and the contents of the pro-
gram memory corresponding to the address is always
regarded as “0” and the contents of the program memory cor-
FPGA/CPLD
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