TMPN3120FE5M
TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TMPN3120FE5M
Neuron
®
Chip
For Distributed Intelligent Control Networks (L
ON
W
ORKS
®
)
The Neuron Chip TMPN3120FE5M provides double the
performance of previous Neuron Chips. It supports a response
time of 3 to 4 ms across a L
ON
W
ORKS
Network and has double
the input / output ( I / O ) performance of the previous Neuron
Chip in terms of both response time and data transmission speed.
The TMPN3120FE5M features an extra single-chip memory in the
form of 3 Kbytes EEPROM, 4 Kbytes SRAM and 16 Kbytes ROM.
It is therefore suitable for applications which require more
complex operations and high speed communication control.
Neuron Chips have all the built-in communications and control
functions required to implement L
ON
W
ORKS
nodes.
These nodes may then be easily integrated into highly-reliable
distributed intelligent control networks.
The typical functions for this chip are explained below.
FEATURES
New features
( In comparison with TMPN3120E1M and TMPN3120FE5M )
•
High-impedance communication port
•
3 Kbytes EEPROM
•
4 Kbytes static RAM
Weight: 1.1g (Typ.)
000707EBA1
•
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the
buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and
to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or
damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the
most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling
Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
•
The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy
control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document
shall be made at the customer’s own risk.
•
The products described in this document are subject to the foreign exchange and foreign trade laws.
•
The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its
use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or
others.
•
The information contained herein is subject to change without notice.
2001-02-21
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TMPN3120FE5M
Main features of the 20 MHz Neuron Chip
( In comparison with the TMPN3120E1M and TMPN3120FE5M )
•
Increased communication speed
The maximum transmission speed has been increased two-fold.
1.25 Mbps
→
2.5 Mbps (*1)
*1: This value applies to Single-Ended Mode only.
•
Shortened response time
The amount of time required from I / O input to I / O output has been greatly reduced.
Maximum speed 7 ms
→
3 ~ 4 ms
•
Increased IO object speed
The execution time for all objects has been halved.
Example ) Serial I / O 9600 bps
Parallel I / O 1.2 µs / byte
•
Development tool support
The current LonBuilder
®
and NodeBuilder
®
development tools can be used to develop applications for
the TMPN3120FE5M (L.B ver 3.01 is needed.). Updated symbol table files for the Neuron Chip firmware
are available from Echelon. If your application requires a 20 MHz input clock, a utility program
available from Echelon may be used to convert the programmer files
*
The conversion utilities can be obtained from the Echelon Web Site at http://www.echelon.com.
I / O Functions
•
Eleven programmable I / O pins.
•
Two programmable 16-bit timers and counters built in.
•
34 different types of I / O functions to handle a wide range of input and output.
•
ROM firmware image containing pre-programmed I / O drivers, greatly simplifying application programs.
Network functions
•
Two CPUs for communication protocol processing built in.
The communications and application CPUs execute in parallel.
•
Equipped with a built-in LonTalk protocol which supports all seven levels of the OSI reference model with
ISO.
•
The ROM firmware image contains a complete network operating system, greatly simplifying application
programs.
•
Built-in twisted-pair wire transceiver with improved common mode and drive current capabilities.
•
Equipped with communications modes and communication speeds which support various types of external
transceivers.
Supports twisted-pair wire, power line, radio ( RF ), infrared, coaxial cables, and fiber optics.
•
Communication port transceiver modes and logical addresses stored within the EEPROM.
Can be amended via the network.
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TMPN3120FE5M
Other functions
•
Application programs are also stored within the EEPROM.
Can be updated by downloading over the network.
•
Built-in watch-dog timer.
•
Each chip has a unique ID number.
Effective during the logical installation of networks.
•
Low electrical consumption mode supported with a sleep mode.
•
Built in Selectable Reset time
Prolongs the power-ON reset time for at least 50 ms and keeps the operation stable during that time. The
reset time can be selected 50ms delay mode or 3 clock delay mode by program after the device is in
power-ON.
•
High-impedance communication port ( CP0 to CP3 )
The Communication port pins ( CP0 to CP3 ) attain high impedance. This eliminates the need for an external
relay.
•
Built-in low-voltage detection circuit.
Prevents incorrect operations and writing errors in the EEPROM during drops in power voltage.
An external LVD must be used to assert reset at power supply voltage below 4.5 V if Neuron Chip is operated
at 20 MHz.
•
Programmable LVD (Low Voltage Detection) circuit.
LVDin pin is prepared in order to make it reset on arbitrary voltage.
•
Firmware version 10.
Timing for the main I / O objects during 20 MHz Neuron Chip operations
I / O MODEL
Parallel
Bitshift
Magcard
Magtrack1
Neurowire Master
Neurowire Slave
Serial
Touch
Frequency Output
10 MHz TIMING
2.4µs / byte
1, 10 or 15 kbps
Up to 8334 bps
Up to 7246 bps
1, 10 or 20 kbps
Up to 18 kbps
600, 1200, 2400 or 4800 bps
Supported
Resolution0.4 to 51.2µs
Max Range 26.21 to 3355 ms
Resolution0.2 to 25.6µs
Max Range 13.1 to 1678 ms
20 MHz TIMING
1.2µs / byte
2, 20 or 30 kbps
Up to 16668 bps
Up to 14492 bps
2, 20 or 40 kbps
Up to 36 kbps
1200, 2400, 4800 or 9600 bps
Not supported
Resolution0.2 to 25.6µs
Max Range 13.1 to 1678 ms
Resolution0.1 to 12.8µs
Max Range 6.55 to 839 ms
Other Timer / Counter
The specifications for the main timers during 20 MHz
operations are as follows :
Watchdog Timer
Millisecond Timers
Second Timers
Delay ( ) Function
Get_Tick_Count ( )
Function
420 ms
1 to 32000 ms
1 to 65000 s
1 to 32767 counts
409.6µs per count
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TMPN3120FE5M
BLOCK DIAGRAM
ITEM
CPU
RAM
ROM
EEPROM
16-bit Timer / Counter
External Memory Interface
Package
TMPN3120FE5M
8-bit CPU × 3
4,096 bytes
16,384 bytes
3,072 bytes
2 channels
Not available
32-pin SOP
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4/11
TMPN3120FE5M
PIN CONNECTION
2001-02-21
5/11
嵌入式系统
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